diff options
Diffstat (limited to 'include/asm-mips/sibyte/sb1250_genbus.h')
| -rw-r--r-- | include/asm-mips/sibyte/sb1250_genbus.h | 322 |
1 files changed, 161 insertions, 161 deletions
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h index 1b5cbc5c6454..94e9c7c8e783 100644 --- a/include/asm-mips/sibyte/sb1250_genbus.h +++ b/include/asm-mips/sibyte/sb1250_genbus.h | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | * | 11 | * |
| 12 | ********************************************************************* | 12 | ********************************************************************* |
| 13 | * | 13 | * |
| 14 | * Copyright 2000,2001,2002,2003 | 14 | * Copyright 2000, 2001, 2002, 2003 |
| 15 | * Broadcom Corporation. All rights reserved. | 15 | * Broadcom Corporation. All rights reserved. |
| 16 | * | 16 | * |
| 17 | * This program is free software; you can redistribute it and/or | 17 | * This program is free software; you can redistribute it and/or |
| @@ -47,7 +47,7 @@ | |||
| 47 | #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) | 47 | #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) |
| 48 | 48 | ||
| 49 | #define S_IO_WIDTH_SEL 2 | 49 | #define S_IO_WIDTH_SEL 2 |
| 50 | #define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) | 50 | #define M_IO_WIDTH_SEL _SB_MAKEMASK(2, S_IO_WIDTH_SEL) |
| 51 | #define K_IO_WIDTH_SEL_1 0 | 51 | #define K_IO_WIDTH_SEL_1 0 |
| 52 | #define K_IO_WIDTH_SEL_2 1 | 52 | #define K_IO_WIDTH_SEL_2 1 |
| 53 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ | 53 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ |
| @@ -55,8 +55,8 @@ | |||
| 55 | #define K_IO_WIDTH_SEL_1L 2 | 55 | #define K_IO_WIDTH_SEL_1L 2 |
| 56 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | 56 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 57 | #define K_IO_WIDTH_SEL_4 3 | 57 | #define K_IO_WIDTH_SEL_4 3 |
| 58 | #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) | 58 | #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL) |
| 59 | #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) | 59 | #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL) |
| 60 | 60 | ||
| 61 | #define S_IO_PARITY_ENA 4 | 61 | #define S_IO_PARITY_ENA 4 |
| 62 | #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) | 62 | #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) |
| @@ -71,18 +71,18 @@ | |||
| 71 | #define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) | 71 | #define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) |
| 72 | 72 | ||
| 73 | #define S_IO_TIMEOUT 8 | 73 | #define S_IO_TIMEOUT 8 |
| 74 | #define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT) | 74 | #define M_IO_TIMEOUT _SB_MAKEMASK(8, S_IO_TIMEOUT) |
| 75 | #define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT) | 75 | #define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT) |
| 76 | #define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT) | 76 | #define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT) |
| 77 | 77 | ||
| 78 | /* | 78 | /* |
| 79 | * Generic Bus Region Size register (Table 11-5) | 79 | * Generic Bus Region Size register (Table 11-5) |
| 80 | */ | 80 | */ |
| 81 | 81 | ||
| 82 | #define S_IO_MULT_SIZE 0 | 82 | #define S_IO_MULT_SIZE 0 |
| 83 | #define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE) | 83 | #define M_IO_MULT_SIZE _SB_MAKEMASK(12, S_IO_MULT_SIZE) |
| 84 | #define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE) | 84 | #define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE) |
| 85 | #define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE) | 85 | #define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE) |
| 86 | 86 | ||
| 87 | #define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ | 87 | #define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ |
| 88 | 88 | ||
| @@ -91,9 +91,9 @@ | |||
| 91 | */ | 91 | */ |
| 92 | 92 | ||
| 93 | #define S_IO_START_ADDR 0 | 93 | #define S_IO_START_ADDR 0 |
| 94 | #define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR) | 94 | #define M_IO_START_ADDR _SB_MAKEMASK(14, S_IO_START_ADDR) |
| 95 | #define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR) | 95 | #define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR) |
| 96 | #define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR) | 96 | #define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR) |
| 97 | 97 | ||
| 98 | #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ | 98 | #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ |
| 99 | 99 | ||
| @@ -105,9 +105,9 @@ | |||
| 105 | */ | 105 | */ |
| 106 | 106 | ||
| 107 | #define S_IO_ALE_WIDTH 0 | 107 | #define S_IO_ALE_WIDTH 0 |
| 108 | #define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH) | 108 | #define M_IO_ALE_WIDTH _SB_MAKEMASK(3, S_IO_ALE_WIDTH) |
| 109 | #define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) | 109 | #define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_ALE_WIDTH) |
| 110 | #define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) | 110 | #define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH) |
| 111 | 111 | ||
| 112 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ | 112 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ |
| 113 | || SIBYTE_HDR_FEATURE_CHIP(1480) | 113 | || SIBYTE_HDR_FEATURE_CHIP(1480) |
| @@ -115,27 +115,27 @@ | |||
| 115 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | 115 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 116 | 116 | ||
| 117 | #define S_IO_ALE_TO_CS 4 | 117 | #define S_IO_ALE_TO_CS 4 |
| 118 | #define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) | 118 | #define M_IO_ALE_TO_CS _SB_MAKEMASK(2, S_IO_ALE_TO_CS) |
| 119 | #define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) | 119 | #define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_CS) |
| 120 | #define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) | 120 | #define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS) |
| 121 | 121 | ||
| 122 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ | 122 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ |
| 123 | || SIBYTE_HDR_FEATURE_CHIP(1480) | 123 | || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 124 | #define S_IO_BURST_WIDTH _SB_MAKE64(6) | 124 | #define S_IO_BURST_WIDTH _SB_MAKE64(6) |
| 125 | #define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) | 125 | #define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH) |
| 126 | #define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) | 126 | #define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH) |
| 127 | #define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) | 127 | #define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH) |
| 128 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | 128 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 129 | 129 | ||
| 130 | #define S_IO_CS_WIDTH 8 | 130 | #define S_IO_CS_WIDTH 8 |
| 131 | #define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) | 131 | #define M_IO_CS_WIDTH _SB_MAKEMASK(5, S_IO_CS_WIDTH) |
| 132 | #define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH) | 132 | #define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x, S_IO_CS_WIDTH) |
| 133 | #define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH) | 133 | #define G_IO_CS_WIDTH(x) _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH) |
| 134 | 134 | ||
| 135 | #define S_IO_RDY_SMPLE 13 | 135 | #define S_IO_RDY_SMPLE 13 |
| 136 | #define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE) | 136 | #define M_IO_RDY_SMPLE _SB_MAKEMASK(3, S_IO_RDY_SMPLE) |
| 137 | #define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE) | 137 | #define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x, S_IO_RDY_SMPLE) |
| 138 | #define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE) | 138 | #define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE) |
| 139 | 139 | ||
| 140 | 140 | ||
| 141 | /* | 141 | /* |
| @@ -143,9 +143,9 @@ | |||
| 143 | */ | 143 | */ |
| 144 | 144 | ||
| 145 | #define S_IO_ALE_TO_WRITE 0 | 145 | #define S_IO_ALE_TO_WRITE 0 |
| 146 | #define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE) | 146 | #define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE) |
| 147 | #define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) | 147 | #define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE) |
| 148 | #define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) | 148 | #define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE) |
| 149 | 149 | ||
| 150 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ | 150 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ |
| 151 | || SIBYTE_HDR_FEATURE_CHIP(1480) | 151 | || SIBYTE_HDR_FEATURE_CHIP(1480) |
| @@ -153,30 +153,30 @@ | |||
| 153 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | 153 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 154 | 154 | ||
| 155 | #define S_IO_WRITE_WIDTH 4 | 155 | #define S_IO_WRITE_WIDTH 4 |
| 156 | #define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) | 156 | #define M_IO_WRITE_WIDTH _SB_MAKEMASK(4, S_IO_WRITE_WIDTH) |
| 157 | #define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH) | 157 | #define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH) |
| 158 | #define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH) | 158 | #define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH) |
| 159 | 159 | ||
| 160 | #define S_IO_IDLE_CYCLE 8 | 160 | #define S_IO_IDLE_CYCLE 8 |
| 161 | #define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE) | 161 | #define M_IO_IDLE_CYCLE _SB_MAKEMASK(4, S_IO_IDLE_CYCLE) |
| 162 | #define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE) | 162 | #define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE) |
| 163 | #define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE) | 163 | #define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE) |
| 164 | 164 | ||
| 165 | #define S_IO_OE_TO_CS 12 | 165 | #define S_IO_OE_TO_CS 12 |
| 166 | #define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS) | 166 | #define M_IO_OE_TO_CS _SB_MAKEMASK(2, S_IO_OE_TO_CS) |
| 167 | #define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS) | 167 | #define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_OE_TO_CS) |
| 168 | #define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS) | 168 | #define G_IO_OE_TO_CS(x) _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS) |
| 169 | 169 | ||
| 170 | #define S_IO_CS_TO_OE 14 | 170 | #define S_IO_CS_TO_OE 14 |
| 171 | #define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE) | 171 | #define M_IO_CS_TO_OE _SB_MAKEMASK(2, S_IO_CS_TO_OE) |
| 172 | #define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE) | 172 | #define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x, S_IO_CS_TO_OE) |
| 173 | #define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE) | 173 | #define G_IO_CS_TO_OE(x) _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE) |
| 174 | 174 | ||
| 175 | /* | 175 | /* |
| 176 | * Generic Bus Interrupt Status Register (Table 11-9) | 176 | * Generic Bus Interrupt Status Register (Table 11-9) |
| 177 | */ | 177 | */ |
| 178 | 178 | ||
| 179 | #define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8) | 179 | #define M_IO_CS_ERR_INT _SB_MAKEMASK(0, 8) |
| 180 | #define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) | 180 | #define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) |
| 181 | #define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) | 181 | #define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) |
| 182 | #define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) | 182 | #define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) |
| @@ -200,116 +200,116 @@ | |||
| 200 | */ | 200 | */ |
| 201 | 201 | ||
| 202 | #define S_IO_SLEW0 0 | 202 | #define S_IO_SLEW0 0 |
| 203 | #define M_IO_SLEW0 _SB_MAKEMASK(2,S_IO_SLEW0) | 203 | #define M_IO_SLEW0 _SB_MAKEMASK(2, S_IO_SLEW0) |
| 204 | #define V_IO_SLEW0(x) _SB_MAKEVALUE(x,S_IO_SLEW0) | 204 | #define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0) |
| 205 | #define G_IO_SLEW0(x) _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0) | 205 | #define G_IO_SLEW0(x) _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0) |
| 206 | 206 | ||
| 207 | #define S_IO_DRV_A 2 | 207 | #define S_IO_DRV_A 2 |
| 208 | #define M_IO_DRV_A _SB_MAKEMASK(2,S_IO_DRV_A) | 208 | #define M_IO_DRV_A _SB_MAKEMASK(2, S_IO_DRV_A) |
| 209 | #define V_IO_DRV_A(x) _SB_MAKEVALUE(x,S_IO_DRV_A) | 209 | #define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A) |
| 210 | #define G_IO_DRV_A(x) _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A) | 210 | #define G_IO_DRV_A(x) _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A) |
| 211 | 211 | ||
| 212 | #define S_IO_DRV_B 6 | 212 | #define S_IO_DRV_B 6 |
| 213 | #define M_IO_DRV_B _SB_MAKEMASK(2,S_IO_DRV_B) | 213 | #define M_IO_DRV_B _SB_MAKEMASK(2, S_IO_DRV_B) |
| 214 | #define V_IO_DRV_B(x) _SB_MAKEVALUE(x,S_IO_DRV_B) | 214 | #define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B) |
| 215 | #define G_IO_DRV_B(x) _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B) | 215 | #define G_IO_DRV_B(x) _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B) |
| 216 | 216 | ||
| 217 | #define S_IO_DRV_C 10 | 217 | #define S_IO_DRV_C 10 |
| 218 | #define M_IO_DRV_C _SB_MAKEMASK(2,S_IO_DRV_C) | 218 | #define M_IO_DRV_C _SB_MAKEMASK(2, S_IO_DRV_C) |
| 219 | #define V_IO_DRV_C(x) _SB_MAKEVALUE(x,S_IO_DRV_C) | 219 | #define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C) |
| 220 | #define G_IO_DRV_C(x) _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C) | 220 | #define G_IO_DRV_C(x) _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C) |
| 221 | 221 | ||
| 222 | #define S_IO_DRV_D 14 | 222 | #define S_IO_DRV_D 14 |
| 223 | #define M_IO_DRV_D _SB_MAKEMASK(2,S_IO_DRV_D) | 223 | #define M_IO_DRV_D _SB_MAKEMASK(2, S_IO_DRV_D) |
| 224 | #define V_IO_DRV_D(x) _SB_MAKEVALUE(x,S_IO_DRV_D) | 224 | #define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D) |
| 225 | #define G_IO_DRV_D(x) _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D) | 225 | #define G_IO_DRV_D(x) _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D) |
| 226 | 226 | ||
| 227 | /* | 227 | /* |
| 228 | * Generic Bus Output Drive Control Register 1 (Table 14-19) | 228 | * Generic Bus Output Drive Control Register 1 (Table 14-19) |
| 229 | */ | 229 | */ |
| 230 | 230 | ||
| 231 | #define S_IO_DRV_E 2 | 231 | #define S_IO_DRV_E 2 |
| 232 | #define M_IO_DRV_E _SB_MAKEMASK(2,S_IO_DRV_E) | 232 | #define M_IO_DRV_E _SB_MAKEMASK(2, S_IO_DRV_E) |
| 233 | #define V_IO_DRV_E(x) _SB_MAKEVALUE(x,S_IO_DRV_E) | 233 | #define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E) |
| 234 | #define G_IO_DRV_E(x) _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E) | 234 | #define G_IO_DRV_E(x) _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E) |
| 235 | 235 | ||
| 236 | #define S_IO_DRV_F 6 | 236 | #define S_IO_DRV_F 6 |
| 237 | #define M_IO_DRV_F _SB_MAKEMASK(2,S_IO_DRV_F) | 237 | #define M_IO_DRV_F _SB_MAKEMASK(2, S_IO_DRV_F) |
| 238 | #define V_IO_DRV_F(x) _SB_MAKEVALUE(x,S_IO_DRV_F) | 238 | #define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F) |
| 239 | #define G_IO_DRV_F(x) _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F) | 239 | #define G_IO_DRV_F(x) _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F) |
| 240 | 240 | ||
| 241 | #define S_IO_SLEW1 8 | 241 | #define S_IO_SLEW1 8 |
| 242 | #define M_IO_SLEW1 _SB_MAKEMASK(2,S_IO_SLEW1) | 242 | #define M_IO_SLEW1 _SB_MAKEMASK(2, S_IO_SLEW1) |
| 243 | #define V_IO_SLEW1(x) _SB_MAKEVALUE(x,S_IO_SLEW1) | 243 | #define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1) |
| 244 | #define G_IO_SLEW1(x) _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1) | 244 | #define G_IO_SLEW1(x) _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1) |
| 245 | 245 | ||
| 246 | #define S_IO_DRV_G 10 | 246 | #define S_IO_DRV_G 10 |
| 247 | #define M_IO_DRV_G _SB_MAKEMASK(2,S_IO_DRV_G) | 247 | #define M_IO_DRV_G _SB_MAKEMASK(2, S_IO_DRV_G) |
| 248 | #define V_IO_DRV_G(x) _SB_MAKEVALUE(x,S_IO_DRV_G) | 248 | #define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G) |
| 249 | #define G_IO_DRV_G(x) _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G) | 249 | #define G_IO_DRV_G(x) _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G) |
| 250 | 250 | ||
| 251 | #define S_IO_SLEW2 12 | 251 | #define S_IO_SLEW2 12 |
| 252 | #define M_IO_SLEW2 _SB_MAKEMASK(2,S_IO_SLEW2) | 252 | #define M_IO_SLEW2 _SB_MAKEMASK(2, S_IO_SLEW2) |
| 253 | #define V_IO_SLEW2(x) _SB_MAKEVALUE(x,S_IO_SLEW2) | 253 | #define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2) |
| 254 | #define G_IO_SLEW2(x) _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2) | 254 | #define G_IO_SLEW2(x) _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2) |
| 255 | 255 | ||
| 256 | #define S_IO_DRV_H 14 | 256 | #define S_IO_DRV_H 14 |
| 257 | #define M_IO_DRV_H _SB_MAKEMASK(2,S_IO_DRV_H) | 257 | #define M_IO_DRV_H _SB_MAKEMASK(2, S_IO_DRV_H) |
| 258 | #define V_IO_DRV_H(x) _SB_MAKEVALUE(x,S_IO_DRV_H) | 258 | #define V_IO_DRV_H(x) _SB_MAKEVALUE(x, S_IO_DRV_H) |
| 259 | #define G_IO_DRV_H(x) _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H) | 259 | #define G_IO_DRV_H(x) _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H) |
| 260 | 260 | ||
| 261 | /* | 261 | /* |
| 262 | * Generic Bus Output Drive Control Register 2 (Table 14-20) | 262 | * Generic Bus Output Drive Control Register 2 (Table 14-20) |
| 263 | */ | 263 | */ |
| 264 | 264 | ||
| 265 | #define S_IO_DRV_J 2 | 265 | #define S_IO_DRV_J 2 |
| 266 | #define M_IO_DRV_J _SB_MAKEMASK(2,S_IO_DRV_J) | 266 | #define M_IO_DRV_J _SB_MAKEMASK(2, S_IO_DRV_J) |
| 267 | #define V_IO_DRV_J(x) _SB_MAKEVALUE(x,S_IO_DRV_J) | 267 | #define V_IO_DRV_J(x) _SB_MAKEVALUE(x, S_IO_DRV_J) |
| 268 | #define G_IO_DRV_J(x) _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J) | 268 | #define G_IO_DRV_J(x) _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J) |
| 269 | 269 | ||
| 270 | #define S_IO_DRV_K 6 | 270 | #define S_IO_DRV_K 6 |
| 271 | #define M_IO_DRV_K _SB_MAKEMASK(2,S_IO_DRV_K) | 271 | #define M_IO_DRV_K _SB_MAKEMASK(2, S_IO_DRV_K) |
| 272 | #define V_IO_DRV_K(x) _SB_MAKEVALUE(x,S_IO_DRV_K) | 272 | #define V_IO_DRV_K(x) _SB_MAKEVALUE(x, S_IO_DRV_K) |
| 273 | #define G_IO_DRV_K(x) _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K) | 273 | #define G_IO_DRV_K(x) _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K) |
| 274 | 274 | ||
| 275 | #define S_IO_DRV_L 10 | 275 | #define S_IO_DRV_L 10 |
| 276 | #define M_IO_DRV_L _SB_MAKEMASK(2,S_IO_DRV_L) | 276 | #define M_IO_DRV_L _SB_MAKEMASK(2, S_IO_DRV_L) |
| 277 | #define V_IO_DRV_L(x) _SB_MAKEVALUE(x,S_IO_DRV_L) | 277 | #define V_IO_DRV_L(x) _SB_MAKEVALUE(x, S_IO_DRV_L) |
| 278 | #define G_IO_DRV_L(x) _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L) | 278 | #define G_IO_DRV_L(x) _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L) |
| 279 | 279 | ||
| 280 | #define S_IO_DRV_M 14 | 280 | #define S_IO_DRV_M 14 |
| 281 | #define M_IO_DRV_M _SB_MAKEMASK(2,S_IO_DRV_M) | 281 | #define M_IO_DRV_M _SB_MAKEMASK(2, S_IO_DRV_M) |
| 282 | #define V_IO_DRV_M(x) _SB_MAKEVALUE(x,S_IO_DRV_M) | 282 | #define V_IO_DRV_M(x) _SB_MAKEVALUE(x, S_IO_DRV_M) |
| 283 | #define G_IO_DRV_M(x) _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M) | 283 | #define G_IO_DRV_M(x) _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M) |
| 284 | 284 | ||
| 285 | /* | 285 | /* |
| 286 | * Generic Bus Output Drive Control Register 3 (Table 14-21) | 286 | * Generic Bus Output Drive Control Register 3 (Table 14-21) |
| 287 | */ | 287 | */ |
| 288 | 288 | ||
| 289 | #define S_IO_SLEW3 0 | 289 | #define S_IO_SLEW3 0 |
| 290 | #define M_IO_SLEW3 _SB_MAKEMASK(2,S_IO_SLEW3) | 290 | #define M_IO_SLEW3 _SB_MAKEMASK(2, S_IO_SLEW3) |
| 291 | #define V_IO_SLEW3(x) _SB_MAKEVALUE(x,S_IO_SLEW3) | 291 | #define V_IO_SLEW3(x) _SB_MAKEVALUE(x, S_IO_SLEW3) |
| 292 | #define G_IO_SLEW3(x) _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3) | 292 | #define G_IO_SLEW3(x) _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3) |
| 293 | 293 | ||
| 294 | #define S_IO_DRV_N 2 | 294 | #define S_IO_DRV_N 2 |
| 295 | #define M_IO_DRV_N _SB_MAKEMASK(2,S_IO_DRV_N) | 295 | #define M_IO_DRV_N _SB_MAKEMASK(2, S_IO_DRV_N) |
| 296 | #define V_IO_DRV_N(x) _SB_MAKEVALUE(x,S_IO_DRV_N) | 296 | #define V_IO_DRV_N(x) _SB_MAKEVALUE(x, S_IO_DRV_N) |
| 297 | #define G_IO_DRV_N(x) _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N) | 297 | #define G_IO_DRV_N(x) _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N) |
| 298 | 298 | ||
| 299 | #define S_IO_DRV_P 6 | 299 | #define S_IO_DRV_P 6 |
| 300 | #define M_IO_DRV_P _SB_MAKEMASK(2,S_IO_DRV_P) | 300 | #define M_IO_DRV_P _SB_MAKEMASK(2, S_IO_DRV_P) |
| 301 | #define V_IO_DRV_P(x) _SB_MAKEVALUE(x,S_IO_DRV_P) | 301 | #define V_IO_DRV_P(x) _SB_MAKEVALUE(x, S_IO_DRV_P) |
| 302 | #define G_IO_DRV_P(x) _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P) | 302 | #define G_IO_DRV_P(x) _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P) |
| 303 | 303 | ||
| 304 | #define S_IO_DRV_Q 10 | 304 | #define S_IO_DRV_Q 10 |
| 305 | #define M_IO_DRV_Q _SB_MAKEMASK(2,S_IO_DRV_Q) | 305 | #define M_IO_DRV_Q _SB_MAKEMASK(2, S_IO_DRV_Q) |
| 306 | #define V_IO_DRV_Q(x) _SB_MAKEVALUE(x,S_IO_DRV_Q) | 306 | #define V_IO_DRV_Q(x) _SB_MAKEVALUE(x, S_IO_DRV_Q) |
| 307 | #define G_IO_DRV_Q(x) _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q) | 307 | #define G_IO_DRV_Q(x) _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q) |
| 308 | 308 | ||
| 309 | #define S_IO_DRV_R 14 | 309 | #define S_IO_DRV_R 14 |
| 310 | #define M_IO_DRV_R _SB_MAKEMASK(2,S_IO_DRV_R) | 310 | #define M_IO_DRV_R _SB_MAKEMASK(2, S_IO_DRV_R) |
| 311 | #define V_IO_DRV_R(x) _SB_MAKEVALUE(x,S_IO_DRV_R) | 311 | #define V_IO_DRV_R(x) _SB_MAKEVALUE(x, S_IO_DRV_R) |
| 312 | #define G_IO_DRV_R(x) _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R) | 312 | #define G_IO_DRV_R(x) _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R) |
| 313 | 313 | ||
| 314 | 314 | ||
| 315 | /* | 315 | /* |
| @@ -329,9 +329,9 @@ | |||
| 329 | 329 | ||
| 330 | #if SIBYTE_HDR_FEATURE_CHIP(1480) | 330 | #if SIBYTE_HDR_FEATURE_CHIP(1480) |
| 331 | #define S_PCMCIA_MODE 16 | 331 | #define S_PCMCIA_MODE 16 |
| 332 | #define M_PCMCIA_MODE _SB_MAKEMASK(3,S_PCMCIA_MODE) | 332 | #define M_PCMCIA_MODE _SB_MAKEMASK(3, S_PCMCIA_MODE) |
| 333 | #define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x,S_PCMCIA_MODE) | 333 | #define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x, S_PCMCIA_MODE) |
| 334 | #define G_PCMCIA_MODE(x) _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE) | 334 | #define G_PCMCIA_MODE(x) _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE) |
| 335 | 335 | ||
| 336 | #define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ | 336 | #define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ |
| 337 | #define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ | 337 | #define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ |
| @@ -369,49 +369,49 @@ | |||
| 369 | #define K_GPIO_INTR_SPLIT 3 | 369 | #define K_GPIO_INTR_SPLIT 3 |
| 370 | 370 | ||
| 371 | #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) | 371 | #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) |
| 372 | #define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n)) | 372 | #define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n)) |
| 373 | #define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n)) | 373 | #define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n)) |
| 374 | #define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n)) | 374 | #define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n)) |
| 375 | 375 | ||
| 376 | #define S_GPIO_INTR_TYPE0 0 | 376 | #define S_GPIO_INTR_TYPE0 0 |
| 377 | #define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0) | 377 | #define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0) |
| 378 | #define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0) | 378 | #define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0) |
| 379 | #define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0) | 379 | #define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0) |
| 380 | 380 | ||
| 381 | #define S_GPIO_INTR_TYPE2 2 | 381 | #define S_GPIO_INTR_TYPE2 2 |
| 382 | #define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2) | 382 | #define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2) |
| 383 | #define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2) | 383 | #define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2) |
| 384 | #define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2) | 384 | #define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2) |
| 385 | 385 | ||
| 386 | #define S_GPIO_INTR_TYPE4 4 | 386 | #define S_GPIO_INTR_TYPE4 4 |
| 387 | #define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4) | 387 | #define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4) |
| 388 | #define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4) | 388 | #define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4) |
| 389 | #define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4) | 389 | #define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4) |
| 390 | 390 | ||
| 391 | #define S_GPIO_INTR_TYPE6 6 | 391 | #define S_GPIO_INTR_TYPE6 6 |
| 392 | #define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6) | 392 | #define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6) |
| 393 | #define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6) | 393 | #define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6) |
| 394 | #define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6) | 394 | #define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6) |
| 395 | 395 | ||
| 396 | #define S_GPIO_INTR_TYPE8 8 | 396 | #define S_GPIO_INTR_TYPE8 8 |
| 397 | #define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8) | 397 | #define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8) |
| 398 | #define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8) | 398 | #define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8) |
| 399 | #define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8) | 399 | #define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8) |
| 400 | 400 | ||
| 401 | #define S_GPIO_INTR_TYPE10 10 | 401 | #define S_GPIO_INTR_TYPE10 10 |
| 402 | #define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10) | 402 | #define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10) |
| 403 | #define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10) | 403 | #define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10) |
| 404 | #define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10) | 404 | #define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10) |
| 405 | 405 | ||
| 406 | #define S_GPIO_INTR_TYPE12 12 | 406 | #define S_GPIO_INTR_TYPE12 12 |
| 407 | #define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12) | 407 | #define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12) |
| 408 | #define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12) | 408 | #define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12) |
| 409 | #define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12) | 409 | #define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12) |
| 410 | 410 | ||
| 411 | #define S_GPIO_INTR_TYPE14 14 | 411 | #define S_GPIO_INTR_TYPE14 14 |
| 412 | #define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14) | 412 | #define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14) |
| 413 | #define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) | 413 | #define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14) |
| 414 | #define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) | 414 | #define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14) |
| 415 | 415 | ||
| 416 | #if SIBYTE_HDR_FEATURE_CHIP(1480) | 416 | #if SIBYTE_HDR_FEATURE_CHIP(1480) |
| 417 | 417 | ||
| @@ -425,49 +425,49 @@ | |||
| 425 | #define K_GPIO_INTR_UNPRED2 3 | 425 | #define K_GPIO_INTR_UNPRED2 3 |
| 426 | 426 | ||
| 427 | #define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) | 427 | #define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) |
| 428 | #define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n)) | 428 | #define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n)) |
| 429 | #define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n)) | 429 | #define V_GPIO_INTR_ATYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n)) |
| 430 | #define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n)) | 430 | #define G_GPIO_INTR_ATYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n)) |
| 431 | 431 | ||
| 432 | #define S_GPIO_INTR_ATYPE0 0 | 432 | #define S_GPIO_INTR_ATYPE0 0 |
| 433 | #define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0) | 433 | #define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0) |
| 434 | #define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0) | 434 | #define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0) |
| 435 | #define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0) | 435 | #define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0) |
| 436 | 436 | ||
| 437 | #define S_GPIO_INTR_ATYPE2 2 | 437 | #define S_GPIO_INTR_ATYPE2 2 |
| 438 | #define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2) | 438 | #define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2) |
| 439 | #define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2) | 439 | #define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2) |
| 440 | #define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2) | 440 | #define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2) |
| 441 | 441 | ||
| 442 | #define S_GPIO_INTR_ATYPE4 4 | 442 | #define S_GPIO_INTR_ATYPE4 4 |
| 443 | #define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4) | 443 | #define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4) |
| 444 | #define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4) | 444 | #define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4) |
| 445 | #define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4) | 445 | #define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4) |
| 446 | 446 | ||
| 447 | #define S_GPIO_INTR_ATYPE6 6 | 447 | #define S_GPIO_INTR_ATYPE6 6 |
| 448 | #define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6) | 448 | #define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6) |
| 449 | #define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6) | 449 | #define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6) |
| 450 | #define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6) | 450 | #define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6) |
| 451 | 451 | ||
| 452 | #define S_GPIO_INTR_ATYPE8 8 | 452 | #define S_GPIO_INTR_ATYPE8 8 |
| 453 | #define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8) | 453 | #define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8) |
| 454 | #define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8) | 454 | #define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8) |
| 455 | #define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8) | 455 | #define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8) |
| 456 | 456 | ||
| 457 | #define S_GPIO_INTR_ATYPE10 10 | 457 | #define S_GPIO_INTR_ATYPE10 10 |
| 458 | #define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10) | 458 | #define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10) |
| 459 | #define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10) | 459 | #define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10) |
| 460 | #define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10) | 460 | #define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10) |
| 461 | 461 | ||
| 462 | #define S_GPIO_INTR_ATYPE12 12 | 462 | #define S_GPIO_INTR_ATYPE12 12 |
| 463 | #define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12) | 463 | #define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12) |
| 464 | #define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12) | 464 | #define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12) |
| 465 | #define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12) | 465 | #define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12) |
| 466 | 466 | ||
| 467 | #define S_GPIO_INTR_ATYPE14 14 | 467 | #define S_GPIO_INTR_ATYPE14 14 |
| 468 | #define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14) | 468 | #define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14) |
| 469 | #define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14) | 469 | #define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14) |
| 470 | #define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14) | 470 | #define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14) |
| 471 | #endif | 471 | #endif |
| 472 | 472 | ||
| 473 | 473 | ||