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-rw-r--r--include/asm-mips/sibyte/sb1250_dma.h70
1 files changed, 35 insertions, 35 deletions
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
index 3cdb48f50ed0..e6145f524fbd 100644
--- a/include/asm-mips/sibyte/sb1250_dma.h
+++ b/include/asm-mips/sibyte/sb1250_dma.h
@@ -7,9 +7,8 @@
7 * programming the SB1250's DMA controllers, both the data mover 7 * programming the SB1250's DMA controllers, both the data mover
8 * and the Ethernet DMA. 8 * and the Ethernet DMA.
9 * 9 *
10 * SB1250 specification level: User's manual 1/02/02 10 * SB1250 specification level: User's manual 10/21/02
11 * 11 * BCM1280 specification level: User's manual 11/24/03
12 * Author: Mitch Lichtenberg
13 * 12 *
14 ********************************************************************* 13 *********************************************************************
15 * 14 *
@@ -58,17 +57,17 @@
58#define M_DMA_RESERVED1 _SB_MAKEMASK1(2) 57#define M_DMA_RESERVED1 _SB_MAKEMASK1(2)
59 58
60#define S_DMA_DESC_TYPE _SB_MAKE64(1) 59#define S_DMA_DESC_TYPE _SB_MAKE64(1)
61#define M_DMA_DESC_TYPE _SB_MAKE64(2,S_DMA_DESC_TYPE) 60#define M_DMA_DESC_TYPE _SB_MAKEMASK(2,S_DMA_DESC_TYPE)
62#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) 61#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE)
63#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) 62#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE)
64 63
65#define K_DMA_DESC_TYPE_RING_AL 0 64#define K_DMA_DESC_TYPE_RING_AL 0
66#define K_DMA_DESC_TYPE_CHAIN_AL 1 65#define K_DMA_DESC_TYPE_CHAIN_AL 1
67 66
68#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 67#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
69#define K_DMA_DESC_TYPE_RING_UAL_WI 2 68#define K_DMA_DESC_TYPE_RING_UAL_WI 2
70#define K_DMA_DESC_TYPE_RING_UAL_RMW 3 69#define K_DMA_DESC_TYPE_RING_UAL_RMW 3
71#endif /* 1250 PASS3 || 112x PASS1 */ 70#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
72 71
73#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3) 72#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3)
74#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4) 73#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4)
@@ -111,11 +110,11 @@
111#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4) 110#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4)
112#define M_DMA_L2CA _SB_MAKEMASK1(5) 111#define M_DMA_L2CA _SB_MAKEMASK1(5)
113 112
114#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 113#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
115#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6) 114#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6)
116#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6) 115#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6)
117#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) 116#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7)
118#endif /* 1250 PASS3 || 112x PASS1 */ 117#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
119 118
120#define M_DMA_MBZ1 _SB_MAKEMASK(6,15) 119#define M_DMA_MBZ1 _SB_MAKEMASK(6,15)
121 120
@@ -165,14 +164,14 @@
165#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) 164#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40)
166#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) 165#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
167 166
168#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 167#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
169#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) 168#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56)
170#endif /* 1250 PASS3 || 112x PASS1 */ 169#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
171 170
172/* 171/*
173 * Receive Packet Drop Registers 172 * Receive Packet Drop Registers
174 */ 173 */
175#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 174#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
176#define S_DMA_OODLOST_RX _SB_MAKE64(0) 175#define S_DMA_OODLOST_RX _SB_MAKE64(0)
177#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) 176#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX)
178#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) 177#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX)
@@ -180,7 +179,7 @@
180#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) 179#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16)
181#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) 180#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX)
182#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) 181#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX)
183#endif /* 1250 PASS3 || 112x PASS1 */ 182#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
184 183
185/* ********************************************************************* 184/* *********************************************************************
186 * DMA Descriptors 185 * DMA Descriptors
@@ -201,21 +200,21 @@
201 200
202#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) 201#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
203 202
204#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 203#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
205#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) 204#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0)
206#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) 205#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA)
207#endif /* 1250 PASS3 || 112x PASS1 */ 206#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
208 207
209#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) 208#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
210#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) 209#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
211#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) 210#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
212#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) 211#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
213 212
214#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 213#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
215#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) 214#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40)
216#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) 215#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT)
217#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) 216#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT)
218#endif /* 1250 PASS3 || 112x PASS1 */ 217#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
219 218
220#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) 219#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
221#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) 220#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
@@ -235,12 +234,12 @@
235#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) 234#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
236#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) 235#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
237 236
238#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 237#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
239#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) 238#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8)
240#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) 239#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE)
241#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) 240#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE)
242#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) 241#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE)
243#endif /* 1250 PASS3 || 112x PASS1 */ 242#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
244 243
245#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) 244#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
246 245
@@ -255,12 +254,12 @@
255 254
256#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) 255#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
257 256
258#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 257#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
259#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) 258#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48)
260#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) 259#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB)
261#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) 260#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB)
262#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) 261#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB)
263#endif /* 1250 PASS3 || 112x PASS1 */ 262#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
264 263
265#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) 264#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
266#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) 265#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
@@ -282,15 +281,16 @@
282#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) 281#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)
283#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) 282#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)
284 283
285#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 284#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
286/* Note: BADTCPCS is actually in DSCR_B options field */ 285/* Note: This bit is in the DSCR_B options field */
287#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) 286#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0)
288#endif /* 1250 PASS2 || 112x PASS1 */ 287#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
289 288
290#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 289#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
290/* Note: These bits are in the DSCR_B options field */
291#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1) 291#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1)
292#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2) 292#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2)
293#endif /* 1250 PASS3 || 112x PASS1 */ 293#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
294 294
295#define S_DMA_ETHRX_RXCH 53 295#define S_DMA_ETHRX_RXCH 53
296#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) 296#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
@@ -438,7 +438,7 @@
438 M_DM_CUR_DSCR_DSCR_COUNT) 438 M_DM_CUR_DSCR_DSCR_COUNT)
439 439
440 440
441#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 441#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
442/* 442/*
443 * Data Mover Channel Partial Result Registers 443 * Data Mover Channel Partial Result Registers
444 * Register: DM_PARTIAL_0 444 * Register: DM_PARTIAL_0
@@ -459,10 +459,10 @@
459 M_DM_PARTIAL_TCPCS_PARTIAL) 459 M_DM_PARTIAL_TCPCS_PARTIAL)
460 460
461#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) 461#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48)
462#endif /* 1250 PASS3 || 112x PASS1 */ 462#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
463 463
464 464
465#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 465#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
466/* 466/*
467 * Data Mover CRC Definition Registers 467 * Data Mover CRC Definition Registers
468 * Register: CRC_DEF_0 468 * Register: CRC_DEF_0
@@ -479,10 +479,10 @@
479#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) 479#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY)
480#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ 480#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\
481 M_CRC_DEF_CRC_POLY) 481 M_CRC_DEF_CRC_POLY)
482#endif /* 1250 PASS3 || 112x PASS1 */ 482#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
483 483
484 484
485#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 485#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
486/* 486/*
487 * Data Mover CRC/Checksum Definition Registers 487 * Data Mover CRC/Checksum Definition Registers
488 * Register: CTCP_DEF_0 488 * Register: CTCP_DEF_0
@@ -511,7 +511,7 @@
511#define K_CTCP_DEF_CRC_WIDTH_1 2 511#define K_CTCP_DEF_CRC_WIDTH_1 2
512 512
513#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50) 513#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50)
514#endif /* 1250 PASS3 || 112x PASS1 */ 514#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
515 515
516 516
517/* 517/*
@@ -560,12 +560,12 @@
560#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50) 560#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50)
561#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51) 561#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51)
562 562
563#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 563#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
564#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52) 564#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52)
565#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53) 565#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53)
566#endif /* 1250 PASS2 || 112x PASS1 */ 566#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
567 567
568#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 568#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
569#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54) 569#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54)
570#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55) 570#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55)
571#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56) 571#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56)
@@ -574,7 +574,7 @@
574#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59) 574#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59)
575#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60) 575#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60)
576#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) 576#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61)
577#endif /* 1250 PASS3 || 112x PASS1 */ 577#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
578 578
579#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) 579#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61)
580 580
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-23 10:41:52 -0400