diff options
Diffstat (limited to 'include/asm-mips/sibyte/bcm1480_regs.h')
| -rw-r--r-- | include/asm-mips/sibyte/bcm1480_regs.h | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h index 2738c1366f66..b4077bb72611 100644 --- a/include/asm-mips/sibyte/bcm1480_regs.h +++ b/include/asm-mips/sibyte/bcm1480_regs.h | |||
| @@ -87,7 +87,7 @@ | |||
| 87 | #define BCM1480_MC_REGISTER_SPACING 0x1000 | 87 | #define BCM1480_MC_REGISTER_SPACING 0x1000 |
| 88 | 88 | ||
| 89 | #define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) | 89 | #define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) |
| 90 | #define A_BCM1480_MC_REGISTER(ctlid,reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) | 90 | #define A_BCM1480_MC_REGISTER(ctlid, reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) |
| 91 | 91 | ||
| 92 | #define R_BCM1480_MC_CONFIG 0x0000000100 | 92 | #define R_BCM1480_MC_CONFIG 0x0000000100 |
| 93 | #define R_BCM1480_MC_CS_START 0x0000000120 | 93 | #define R_BCM1480_MC_CS_START 0x0000000120 |
| @@ -227,10 +227,15 @@ | |||
| 227 | (A_BCM1480_DUART(chan) + \ | 227 | (A_BCM1480_DUART(chan) + \ |
| 228 | BCM1480_DUART_CHANREG_SPACING * 3 + (reg)) | 228 | BCM1480_DUART_CHANREG_SPACING * 3 + (reg)) |
| 229 | 229 | ||
| 230 | #define DUART_IMRISR_SPACING 0x20 | ||
| 231 | #define DUART_INCHNG_SPACING 0x10 | ||
| 232 | |||
| 230 | #define R_BCM1480_DUART_IMRREG(chan) \ | 233 | #define R_BCM1480_DUART_IMRREG(chan) \ |
| 231 | (R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING) | 234 | (R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING) |
| 232 | #define R_BCM1480_DUART_ISRREG(chan) \ | 235 | #define R_BCM1480_DUART_ISRREG(chan) \ |
| 233 | (R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING) | 236 | (R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING) |
| 237 | #define R_BCM1480_DUART_INCHREG(chan) \ | ||
| 238 | (R_DUART_IN_CHNG_A + ((chan) & 1) * DUART_INCHNG_SPACING) | ||
| 234 | 239 | ||
| 235 | #define A_BCM1480_DUART_IMRREG(chan) \ | 240 | #define A_BCM1480_DUART_IMRREG(chan) \ |
| 236 | (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan))) | 241 | (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan))) |
| @@ -322,7 +327,7 @@ | |||
| 322 | #define BCM1480_SCD_NUM_WDOGS 4 | 327 | #define BCM1480_SCD_NUM_WDOGS 4 |
| 323 | 328 | ||
| 324 | #define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) | 329 | #define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) |
| 325 | #define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) | 330 | #define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) |
| 326 | 331 | ||
| 327 | #define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 | 332 | #define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 |
| 328 | #define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 | 333 | #define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 |
| @@ -367,7 +372,7 @@ | |||
| 367 | #define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 | 372 | #define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 |
| 368 | 373 | ||
| 369 | #define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) | 374 | #define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) |
| 370 | #define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) | 375 | #define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) |
| 371 | 376 | ||
| 372 | /* Most IMR registers are 128 bits, implemented as non-contiguous | 377 | /* Most IMR registers are 128 bits, implemented as non-contiguous |
| 373 | 64-bit registers high (_H) and low (_L) */ | 378 | 64-bit registers high (_H) and low (_L) */ |
| @@ -408,7 +413,7 @@ | |||
| 408 | 413 | ||
| 409 | #define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ | 414 | #define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ |
| 410 | (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) | 415 | (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) |
| 411 | #define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) | 416 | #define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) |
| 412 | 417 | ||
| 413 | #define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ | 418 | #define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ |
| 414 | #define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ | 419 | #define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ |
| @@ -422,7 +427,7 @@ | |||
| 422 | #define R_BCM1480_IMR_MAILBOX_SET 0x08 | 427 | #define R_BCM1480_IMR_MAILBOX_SET 0x08 |
| 423 | #define R_BCM1480_IMR_MAILBOX_CLR 0x10 | 428 | #define R_BCM1480_IMR_MAILBOX_CLR 0x10 |
| 424 | #define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20 | 429 | #define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20 |
| 425 | #define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \ | 430 | #define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \ |
| 426 | (A_BCM1480_IMR_CPU0_BASE + \ | 431 | (A_BCM1480_IMR_CPU0_BASE + \ |
| 427 | (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \ | 432 | (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \ |
| 428 | (cpu * BCM1480_IMR_REGISTER_SPACING) + \ | 433 | (cpu * BCM1480_IMR_REGISTER_SPACING) + \ |
| @@ -545,7 +550,7 @@ | |||
| 545 | #define BCM1480_HR_REGISTER_SPACING 0x80000 | 550 | #define BCM1480_HR_REGISTER_SPACING 0x80000 |
| 546 | 551 | ||
| 547 | #define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) | 552 | #define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) |
| 548 | #define A_BCM1480_HR_REGISTER(idx,reg) (A_BCM1480_HR_BASE(idx) + (reg)) | 553 | #define A_BCM1480_HR_REGISTER(idx, reg) (A_BCM1480_HR_BASE(idx) + (reg)) |
| 549 | 554 | ||
| 550 | #define R_BCM1480_HR_CFG 0x0000000000 | 555 | #define R_BCM1480_HR_CFG 0x0000000000 |
| 551 | 556 | ||
| @@ -594,9 +599,9 @@ | |||
| 594 | #define BCM1480_PM_NUM_CHANNELS 32 | 599 | #define BCM1480_PM_NUM_CHANNELS 32 |
| 595 | 600 | ||
| 596 | #define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) | 601 | #define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) |
| 597 | #define A_BCM1480_PMI_LCL_REGISTER(idx,reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) | 602 | #define A_BCM1480_PMI_LCL_REGISTER(idx, reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) |
| 598 | #define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) | 603 | #define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) |
| 599 | #define A_BCM1480_PMO_LCL_REGISTER(idx,reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) | 604 | #define A_BCM1480_PMO_LCL_REGISTER(idx, reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) |
| 600 | 605 | ||
| 601 | #define BCM1480_PM_INT_PACKING 8 | 606 | #define BCM1480_PM_INT_PACKING 8 |
| 602 | #define BCM1480_PM_INT_FUNCTION_SPACING 0x40 | 607 | #define BCM1480_PM_INT_FUNCTION_SPACING 0x40 |
| @@ -716,7 +721,7 @@ | |||
| 716 | #define BCM1480_HSP_REGISTER_SPACING 0x80000 | 721 | #define BCM1480_HSP_REGISTER_SPACING 0x80000 |
| 717 | 722 | ||
| 718 | #define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) | 723 | #define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) |
| 719 | #define A_BCM1480_HSP_REGISTER(idx,reg) (A_BCM1480_HSP_BASE(idx) + (reg)) | 724 | #define A_BCM1480_HSP_REGISTER(idx, reg) (A_BCM1480_HSP_BASE(idx) + (reg)) |
| 720 | 725 | ||
| 721 | #define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 | 726 | #define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 |
| 722 | #define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 | 727 | #define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 |