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-rw-r--r--include/asm-mips/pgtable-64.h70
1 files changed, 41 insertions, 29 deletions
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index 1011e0635f56..3e0a522c0f0e 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -16,13 +16,15 @@
16#include <asm/page.h> 16#include <asm/page.h>
17#include <asm/cachectl.h> 17#include <asm/cachectl.h>
18 18
19#include <asm-generic/pgtable-nopud.h>
20
19/* 21/*
20 * Each address space has 2 4K pages as its page directory, giving 1024 22 * Each address space has 2 4K pages as its page directory, giving 1024
21 * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a 23 * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
22 * pair of 4K pages, giving 1024 (== PTRS_PER_PMD) 8 byte pointers to 24 * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
23 * page tables. Each page table is a single 4K page, giving 512 (== 25 * tables. Each page table is also a single 4K page, giving 512 (==
24 * PTRS_PER_PTE) 8 byte ptes. Each pgde is initialized to point to 26 * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
25 * invalid_pmd_table, each pmde is initialized to point to 27 * invalid_pmd_table, each pmd entry is initialized to point to
26 * invalid_pte_table, each pte is initialized to 0. When memory is low, 28 * invalid_pte_table, each pte is initialized to 0. When memory is low,
27 * and a pmd table or a page table allocation fails, empty_bad_pmd_table 29 * and a pmd table or a page table allocation fails, empty_bad_pmd_table
28 * and empty_bad_page_table is returned back to higher layer code, so 30 * and empty_bad_page_table is returned back to higher layer code, so
@@ -36,17 +38,17 @@
36 */ 38 */
37 39
38/* PMD_SHIFT determines the size of the area a second-level page table can map */ 40/* PMD_SHIFT determines the size of the area a second-level page table can map */
39#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3)) 41#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
40#define PMD_SIZE (1UL << PMD_SHIFT) 42#define PMD_SIZE (1UL << PMD_SHIFT)
41#define PMD_MASK (~(PMD_SIZE-1)) 43#define PMD_MASK (~(PMD_SIZE-1))
42 44
43/* PGDIR_SHIFT determines what a third-level page table entry can map */ 45/* PGDIR_SHIFT determines what a third-level page table entry can map */
44#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + 1 - 3)) 46#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
45#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 47#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
46#define PGDIR_MASK (~(PGDIR_SIZE-1)) 48#define PGDIR_MASK (~(PGDIR_SIZE-1))
47 49
48/* 50/*
49 * For 4kB page size we use a 3 level page tree and a 8kB pmd and pgds which 51 * For 4kB page size we use a 3 level page tree and an 8kB pud, which
50 * permits us mapping 40 bits of virtual address space. 52 * permits us mapping 40 bits of virtual address space.
51 * 53 *
52 * We used to implement 41 bits by having an order 1 pmd level but that seemed 54 * We used to implement 41 bits by having an order 1 pmd level but that seemed
@@ -57,7 +59,7 @@
57 * two levels would be easy to implement. 59 * two levels would be easy to implement.
58 * 60 *
59 * For 16kB page size we use a 2 level page tree which permits a total of 61 * For 16kB page size we use a 2 level page tree which permits a total of
60 * 36 bits of virtual address space. We could add a third leve. but it seems 62 * 36 bits of virtual address space. We could add a third level but it seems
61 * like at the moment there's no need for this. 63 * like at the moment there's no need for this.
62 * 64 *
63 * For 64kB page size we use a 2 level page table tree for a total of 42 bits 65 * For 64kB page size we use a 2 level page table tree for a total of 42 bits
@@ -65,21 +67,25 @@
65 */ 67 */
66#ifdef CONFIG_PAGE_SIZE_4KB 68#ifdef CONFIG_PAGE_SIZE_4KB
67#define PGD_ORDER 1 69#define PGD_ORDER 1
70#define PUD_ORDER aieeee_attempt_to_allocate_pud
68#define PMD_ORDER 0 71#define PMD_ORDER 0
69#define PTE_ORDER 0 72#define PTE_ORDER 0
70#endif 73#endif
71#ifdef CONFIG_PAGE_SIZE_8KB 74#ifdef CONFIG_PAGE_SIZE_8KB
72#define PGD_ORDER 0 75#define PGD_ORDER 0
76#define PUD_ORDER aieeee_attempt_to_allocate_pud
73#define PMD_ORDER 0 77#define PMD_ORDER 0
74#define PTE_ORDER 0 78#define PTE_ORDER 0
75#endif 79#endif
76#ifdef CONFIG_PAGE_SIZE_16KB 80#ifdef CONFIG_PAGE_SIZE_16KB
77#define PGD_ORDER 0 81#define PGD_ORDER 0
82#define PUD_ORDER aieeee_attempt_to_allocate_pud
78#define PMD_ORDER 0 83#define PMD_ORDER 0
79#define PTE_ORDER 0 84#define PTE_ORDER 0
80#endif 85#endif
81#ifdef CONFIG_PAGE_SIZE_64KB 86#ifdef CONFIG_PAGE_SIZE_64KB
82#define PGD_ORDER 0 87#define PGD_ORDER 0
88#define PUD_ORDER aieeee_attempt_to_allocate_pud
83#define PMD_ORDER 0 89#define PMD_ORDER 0
84#define PTE_ORDER 0 90#define PTE_ORDER 0
85#endif 91#endif
@@ -91,7 +97,7 @@
91#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 97#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
92#define FIRST_USER_ADDRESS 0 98#define FIRST_USER_ADDRESS 0
93 99
94#define VMALLOC_START XKSEG 100#define VMALLOC_START MAP_BASE
95#define VMALLOC_END \ 101#define VMALLOC_END \
96 (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE) 102 (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)
97 103
@@ -102,13 +108,13 @@
102#define pgd_ERROR(e) \ 108#define pgd_ERROR(e) \
103 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 109 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
104 110
105extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)]; 111extern pte_t invalid_pte_table[PTRS_PER_PTE];
106extern pte_t empty_bad_page_table[PAGE_SIZE/sizeof(pte_t)]; 112extern pte_t empty_bad_page_table[PTRS_PER_PTE];
107extern pmd_t invalid_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)]; 113extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
108extern pmd_t empty_bad_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)]; 114extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
109 115
110/* 116/*
111 * Empty pmd entries point to the invalid_pte_table. 117 * Empty pgd/pmd entries point to the invalid_pte_table.
112 */ 118 */
113static inline int pmd_none(pmd_t pmd) 119static inline int pmd_none(pmd_t pmd)
114{ 120{
@@ -128,26 +134,30 @@ static inline void pmd_clear(pmd_t *pmdp)
128} 134}
129 135
130/* 136/*
131 * Empty pgd entries point to the invalid_pmd_table. 137 * Empty pud entries point to the invalid_pmd_table.
132 */ 138 */
133static inline int pgd_none(pgd_t pgd) 139static inline int pud_none(pud_t pud)
134{ 140{
135 return pgd_val(pgd) == (unsigned long) invalid_pmd_table; 141 return pud_val(pud) == (unsigned long) invalid_pmd_table;
136} 142}
137 143
138#define pgd_bad(pgd) (pgd_val(pgd) &~ PAGE_MASK) 144static inline int pud_bad(pud_t pud)
145{
146 return pud_val(pud) & ~PAGE_MASK;
147}
139 148
140static inline int pgd_present(pgd_t pgd) 149static inline int pud_present(pud_t pud)
141{ 150{
142 return pgd_val(pgd) != (unsigned long) invalid_pmd_table; 151 return pud_val(pud) != (unsigned long) invalid_pmd_table;
143} 152}
144 153
145static inline void pgd_clear(pgd_t *pgdp) 154static inline void pud_clear(pud_t *pudp)
146{ 155{
147 pgd_val(*pgdp) = ((unsigned long) invalid_pmd_table); 156 pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
148} 157}
149 158
150#define pte_page(x) pfn_to_page((unsigned long)((pte_val(x) >> PAGE_SHIFT))) 159#define pte_page(x) pfn_to_page(pte_pfn(x))
160
151#ifdef CONFIG_CPU_VR41XX 161#ifdef CONFIG_CPU_VR41XX
152#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) 162#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
153#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) 163#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
@@ -157,26 +167,28 @@ static inline void pgd_clear(pgd_t *pgdp)
157#endif 167#endif
158 168
159#define __pgd_offset(address) pgd_index(address) 169#define __pgd_offset(address) pgd_index(address)
170#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
171#define __pmd_offset(address) pmd_index(address)
160#define page_pte(page) page_pte_prot(page, __pgprot(0)) 172#define page_pte(page) page_pte_prot(page, __pgprot(0))
161 173
162/* to find an entry in a kernel page-table-directory */ 174/* to find an entry in a kernel page-table-directory */
163#define pgd_offset_k(address) pgd_offset(&init_mm, 0) 175#define pgd_offset_k(address) pgd_offset(&init_mm, 0)
164 176
165#define pgd_index(address) ((address) >> PGDIR_SHIFT) 177#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
178#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
166 179
167/* to find an entry in a page-table-directory */ 180/* to find an entry in a page-table-directory */
168#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) 181#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr))
169 182
170static inline unsigned long pgd_page(pgd_t pgd) 183static inline unsigned long pud_page(pud_t pud)
171{ 184{
172 return pgd_val(pgd); 185 return pud_val(pud);
173} 186}
174 187
175/* Find an entry in the second-level page table.. */ 188/* Find an entry in the second-level page table.. */
176static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address) 189static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
177{ 190{
178 return (pmd_t *) pgd_page(*dir) + 191 return (pmd_t *) pud_page(*pud) + pmd_index(address);
179 ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
180} 192}
181 193
182/* Find an entry in the third-level page table.. */ 194/* Find an entry in the third-level page table.. */