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Diffstat (limited to 'include/asm-mips/pgtable-32.h')
-rw-r--r-- | include/asm-mips/pgtable-32.h | 243 |
1 files changed, 243 insertions, 0 deletions
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h new file mode 100644 index 000000000000..41a0df7d7768 --- /dev/null +++ b/include/asm-mips/pgtable-32.h | |||
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1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle | ||
7 | * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. | ||
8 | */ | ||
9 | #ifndef _ASM_PGTABLE_32_H | ||
10 | #define _ASM_PGTABLE_32_H | ||
11 | |||
12 | #include <linux/config.h> | ||
13 | #include <asm/addrspace.h> | ||
14 | #include <asm/page.h> | ||
15 | |||
16 | #include <linux/linkage.h> | ||
17 | #include <asm/cachectl.h> | ||
18 | #include <asm/fixmap.h> | ||
19 | |||
20 | /* | ||
21 | * - add_wired_entry() add a fixed TLB entry, and move wired register | ||
22 | */ | ||
23 | extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, | ||
24 | unsigned long entryhi, unsigned long pagemask); | ||
25 | |||
26 | /* | ||
27 | * - add_temporary_entry() add a temporary TLB entry. We use TLB entries | ||
28 | * starting at the top and working down. This is for populating the | ||
29 | * TLB before trap_init() puts the TLB miss handler in place. It | ||
30 | * should be used only for entries matching the actual page tables, | ||
31 | * to prevent inconsistencies. | ||
32 | */ | ||
33 | extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, | ||
34 | unsigned long entryhi, unsigned long pagemask); | ||
35 | |||
36 | |||
37 | /* Basically we have the same two-level (which is the logical three level | ||
38 | * Linux page table layout folded) page tables as the i386. Some day | ||
39 | * when we have proper page coloring support we can have a 1% quicker | ||
40 | * tlb refill handling mechanism, but for now it is a bit slower but | ||
41 | * works even with the cache aliasing problem the R4k and above have. | ||
42 | */ | ||
43 | |||
44 | /* PMD_SHIFT determines the size of the area a second-level page table can map */ | ||
45 | #ifdef CONFIG_64BIT_PHYS_ADDR | ||
46 | #define PMD_SHIFT 21 | ||
47 | #else | ||
48 | #define PMD_SHIFT 22 | ||
49 | #endif | ||
50 | #define PMD_SIZE (1UL << PMD_SHIFT) | ||
51 | #define PMD_MASK (~(PMD_SIZE-1)) | ||
52 | |||
53 | /* PGDIR_SHIFT determines what a third-level page table entry can map */ | ||
54 | #define PGDIR_SHIFT PMD_SHIFT | ||
55 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | ||
56 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | ||
57 | |||
58 | /* | ||
59 | * Entries per page directory level: we use two-level, so | ||
60 | * we don't really have any PMD directory physically. | ||
61 | */ | ||
62 | #ifdef CONFIG_64BIT_PHYS_ADDR | ||
63 | #define PGD_ORDER 1 | ||
64 | #define PMD_ORDER 0 | ||
65 | #define PTE_ORDER 0 | ||
66 | #else | ||
67 | #define PGD_ORDER 0 | ||
68 | #define PMD_ORDER 0 | ||
69 | #define PTE_ORDER 0 | ||
70 | #endif | ||
71 | |||
72 | #define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) | ||
73 | #define PTRS_PER_PMD 1 | ||
74 | #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) | ||
75 | |||
76 | #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) | ||
77 | #define FIRST_USER_PGD_NR 0 | ||
78 | |||
79 | #define VMALLOC_START KSEG2 | ||
80 | |||
81 | #ifdef CONFIG_HIGHMEM | ||
82 | # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE) | ||
83 | #else | ||
84 | # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) | ||
85 | #endif | ||
86 | |||
87 | #ifdef CONFIG_64BIT_PHYS_ADDR | ||
88 | #define pte_ERROR(e) \ | ||
89 | printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e)) | ||
90 | #else | ||
91 | #define pte_ERROR(e) \ | ||
92 | printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) | ||
93 | #endif | ||
94 | #define pmd_ERROR(e) \ | ||
95 | printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | ||
96 | #define pgd_ERROR(e) \ | ||
97 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | ||
98 | |||
99 | extern void load_pgd(unsigned long pg_dir); | ||
100 | |||
101 | extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)]; | ||
102 | |||
103 | /* | ||
104 | * Empty pgd/pmd entries point to the invalid_pte_table. | ||
105 | */ | ||
106 | static inline int pmd_none(pmd_t pmd) | ||
107 | { | ||
108 | return pmd_val(pmd) == (unsigned long) invalid_pte_table; | ||
109 | } | ||
110 | |||
111 | #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) | ||
112 | |||
113 | static inline int pmd_present(pmd_t pmd) | ||
114 | { | ||
115 | return pmd_val(pmd) != (unsigned long) invalid_pte_table; | ||
116 | } | ||
117 | |||
118 | static inline void pmd_clear(pmd_t *pmdp) | ||
119 | { | ||
120 | pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); | ||
121 | } | ||
122 | |||
123 | /* | ||
124 | * The "pgd_xxx()" functions here are trivial for a folded two-level | ||
125 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | ||
126 | * into the pgd entry) | ||
127 | */ | ||
128 | static inline int pgd_none(pgd_t pgd) { return 0; } | ||
129 | static inline int pgd_bad(pgd_t pgd) { return 0; } | ||
130 | static inline int pgd_present(pgd_t pgd) { return 1; } | ||
131 | static inline void pgd_clear(pgd_t *pgdp) { } | ||
132 | |||
133 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) | ||
134 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | ||
135 | #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) | ||
136 | static inline pte_t | ||
137 | pfn_pte(unsigned long pfn, pgprot_t prot) | ||
138 | { | ||
139 | pte_t pte; | ||
140 | pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f); | ||
141 | pte.pte_low = pgprot_val(prot); | ||
142 | return pte; | ||
143 | } | ||
144 | |||
145 | #else | ||
146 | |||
147 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | ||
148 | |||
149 | #ifdef CONFIG_CPU_VR41XX | ||
150 | #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) | ||
151 | #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) | ||
152 | #else | ||
153 | #define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) | ||
154 | #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) | ||
155 | #endif | ||
156 | #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ | ||
157 | |||
158 | #define __pgd_offset(address) pgd_index(address) | ||
159 | #define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | ||
160 | |||
161 | /* to find an entry in a kernel page-table-directory */ | ||
162 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | ||
163 | |||
164 | #define pgd_index(address) ((address) >> PGDIR_SHIFT) | ||
165 | |||
166 | /* to find an entry in a page-table-directory */ | ||
167 | #define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) | ||
168 | |||
169 | /* Find an entry in the second-level page table.. */ | ||
170 | static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address) | ||
171 | { | ||
172 | return (pmd_t *) dir; | ||
173 | } | ||
174 | |||
175 | /* Find an entry in the third-level page table.. */ | ||
176 | #define __pte_offset(address) \ | ||
177 | (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | ||
178 | #define pte_offset(dir, address) \ | ||
179 | ((pte_t *) (pmd_page_kernel(*dir)) + __pte_offset(address)) | ||
180 | #define pte_offset_kernel(dir, address) \ | ||
181 | ((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(address)) | ||
182 | |||
183 | #define pte_offset_map(dir, address) \ | ||
184 | ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) | ||
185 | #define pte_offset_map_nested(dir, address) \ | ||
186 | ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) | ||
187 | #define pte_unmap(pte) ((void)(pte)) | ||
188 | #define pte_unmap_nested(pte) ((void)(pte)) | ||
189 | |||
190 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) | ||
191 | |||
192 | /* Swap entries must have VALID bit cleared. */ | ||
193 | #define __swp_type(x) (((x).val >> 10) & 0x1f) | ||
194 | #define __swp_offset(x) ((x).val >> 15) | ||
195 | #define __swp_entry(type,offset) \ | ||
196 | ((swp_entry_t) { ((type) << 10) | ((offset) << 15) }) | ||
197 | |||
198 | /* | ||
199 | * Bits 0, 1, 2, 9 and 10 are taken, split up the 27 bits of offset | ||
200 | * into this range: | ||
201 | */ | ||
202 | #define PTE_FILE_MAX_BITS 27 | ||
203 | |||
204 | #define pte_to_pgoff(_pte) \ | ||
205 | ((((_pte).pte >> 3) & 0x3f ) + (((_pte).pte >> 11) << 8 )) | ||
206 | |||
207 | #define pgoff_to_pte(off) \ | ||
208 | ((pte_t) { (((off) & 0x3f) << 3) + (((off) >> 8) << 11) + _PAGE_FILE }) | ||
209 | |||
210 | #else | ||
211 | |||
212 | /* Swap entries must have VALID and GLOBAL bits cleared. */ | ||
213 | #define __swp_type(x) (((x).val >> 8) & 0x1f) | ||
214 | #define __swp_offset(x) ((x).val >> 13) | ||
215 | #define __swp_entry(type,offset) \ | ||
216 | ((swp_entry_t) { ((type) << 8) | ((offset) << 13) }) | ||
217 | |||
218 | /* | ||
219 | * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset | ||
220 | * into this range: | ||
221 | */ | ||
222 | #define PTE_FILE_MAX_BITS 27 | ||
223 | |||
224 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) | ||
225 | /* fixme */ | ||
226 | #define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f)) | ||
227 | #define pgoff_to_pte(off) \ | ||
228 | ((pte_t){(((off) & 0x3f) + ((off) << 6) + _PAGE_FILE)}) | ||
229 | |||
230 | #else | ||
231 | #define pte_to_pgoff(_pte) \ | ||
232 | ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 )) | ||
233 | |||
234 | #define pgoff_to_pte(off) \ | ||
235 | ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE }) | ||
236 | #endif | ||
237 | |||
238 | #endif | ||
239 | |||
240 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | ||
241 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | ||
242 | |||
243 | #endif /* _ASM_PGTABLE_32_H */ | ||