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-rw-r--r--include/asm-mips/mipsregs.h394
1 files changed, 390 insertions, 4 deletions
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 2197aa4ce456..80370e0a5589 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -8,7 +8,7 @@
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2003 Maciej W. Rozycki 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */ 12 */
13#ifndef _ASM_MIPSREGS_H 13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H 14#define _ASM_MIPSREGS_H
@@ -96,6 +96,16 @@
96#define CP0_S1_INTCONTROL $20 96#define CP0_S1_INTCONTROL $20
97 97
98/* 98/*
99 * Coprocessor 0 Set 2 register names
100 */
101#define CP0_S2_SRSCTL $12 /* MIPSR2 */
102
103/*
104 * Coprocessor 0 Set 3 register names
105 */
106#define CP0_S3_SRSMAP $12 /* MIPSR2 */
107
108/*
99 * TX39 Series 109 * TX39 Series
100 */ 110 */
101#define CP0_TX39_CACHE $7 111#define CP0_TX39_CACHE $7
@@ -281,6 +291,11 @@
281#define ST0_DL (_ULCAST_(1) << 24) 291#define ST0_DL (_ULCAST_(1) << 24)
282 292
283/* 293/*
294 * Enable the MIPS DSP ASE
295 */
296#define ST0_MX 0x01000000
297
298/*
284 * Bitfields in the TX39 family CP0 Configuration Register 3 299 * Bitfields in the TX39 family CP0 Configuration Register 3
285 */ 300 */
286#define TX39_CONF_ICS_SHIFT 19 301#define TX39_CONF_ICS_SHIFT 19
@@ -433,6 +448,14 @@
433#define R5K_CONF_SE (_ULCAST_(1) << 12) 448#define R5K_CONF_SE (_ULCAST_(1) << 12)
434#define R5K_CONF_SS (_ULCAST_(3) << 20) 449#define R5K_CONF_SS (_ULCAST_(3) << 20)
435 450
451/* Bits specific to the RM7000. */
452#define RM7K_CONF_SE (_ULCAST_(1) << 3)
453#define RM7K_CONF_TE (_ULCAST_(1) << 12)
454#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
455#define RM7K_CONF_TC (_ULCAST_(1) << 17)
456#define RM7K_CONF_SI (_ULCAST_(3) << 20)
457#define RM7K_CONF_SC (_ULCAST_(1) << 31)
458
436/* Bits specific to the R10000. */ 459/* Bits specific to the R10000. */
437#define R10K_CONF_DN (_ULCAST_(3) << 3) 460#define R10K_CONF_DN (_ULCAST_(3) << 3)
438#define R10K_CONF_CT (_ULCAST_(1) << 5) 461#define R10K_CONF_CT (_ULCAST_(1) << 5)
@@ -475,6 +498,53 @@
475#define MIPS_CONF_M (_ULCAST_(1) << 31) 498#define MIPS_CONF_M (_ULCAST_(1) << 31)
476 499
477/* 500/*
501 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
502 */
503#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
504#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
505#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
506#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
507#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
508#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
509#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
510#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
511#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
512#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
513#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
514#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
515#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
516#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
517
518#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
519#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
520#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
521#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
522#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
523#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
524#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
525#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
526
527#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
528#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
529#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
530#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
531#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
532#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
533#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
534#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
535
536/*
537 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
538 */
539#define MIPS_FPIR_S (_ULCAST_(1) << 16)
540#define MIPS_FPIR_D (_ULCAST_(1) << 17)
541#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
542#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
543#define MIPS_FPIR_W (_ULCAST_(1) << 20)
544#define MIPS_FPIR_L (_ULCAST_(1) << 21)
545#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
546
547/*
478 * R10000 performance counter definitions. 548 * R10000 performance counter definitions.
479 * 549 *
480 * FIXME: The R10000 performance counter opens a nice way to implement CPU 550 * FIXME: The R10000 performance counter opens a nice way to implement CPU
@@ -621,13 +691,13 @@ do { \
621 if (sel == 0) \ 691 if (sel == 0) \
622 __asm__ __volatile__( \ 692 __asm__ __volatile__( \
623 "mtc0\t%z0, " #register "\n\t" \ 693 "mtc0\t%z0, " #register "\n\t" \
624 : : "Jr" ((unsigned int)value)); \ 694 : : "Jr" ((unsigned int)(value))); \
625 else \ 695 else \
626 __asm__ __volatile__( \ 696 __asm__ __volatile__( \
627 ".set\tmips32\n\t" \ 697 ".set\tmips32\n\t" \
628 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 698 "mtc0\t%z0, " #register ", " #sel "\n\t" \
629 ".set\tmips0" \ 699 ".set\tmips0" \
630 : : "Jr" ((unsigned int)value)); \ 700 : : "Jr" ((unsigned int)(value))); \
631} while (0) 701} while (0)
632 702
633#define __write_64bit_c0_register(register, sel, value) \ 703#define __write_64bit_c0_register(register, sel, value) \
@@ -676,7 +746,7 @@ do { \
676do { \ 746do { \
677 __asm__ __volatile__( \ 747 __asm__ __volatile__( \
678 "ctc0\t%z0, " #register "\n\t" \ 748 "ctc0\t%z0, " #register "\n\t" \
679 : : "Jr" ((unsigned int)value)); \ 749 : : "Jr" ((unsigned int)(value))); \
680} while (0) 750} while (0)
681 751
682/* 752/*
@@ -769,12 +839,24 @@ do { \
769#define read_c0_count() __read_32bit_c0_register($9, 0) 839#define read_c0_count() __read_32bit_c0_register($9, 0)
770#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 840#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
771 841
842#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
843#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
844
845#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
846#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
847
772#define read_c0_entryhi() __read_ulong_c0_register($10, 0) 848#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
773#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 849#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
774 850
775#define read_c0_compare() __read_32bit_c0_register($11, 0) 851#define read_c0_compare() __read_32bit_c0_register($11, 0)
776#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 852#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
777 853
854#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
855#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
856
857#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
858#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
859
778#define read_c0_status() __read_32bit_c0_register($12, 0) 860#define read_c0_status() __read_32bit_c0_register($12, 0)
779#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 861#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
780 862
@@ -790,10 +872,18 @@ do { \
790#define read_c0_config1() __read_32bit_c0_register($16, 1) 872#define read_c0_config1() __read_32bit_c0_register($16, 1)
791#define read_c0_config2() __read_32bit_c0_register($16, 2) 873#define read_c0_config2() __read_32bit_c0_register($16, 2)
792#define read_c0_config3() __read_32bit_c0_register($16, 3) 874#define read_c0_config3() __read_32bit_c0_register($16, 3)
875#define read_c0_config4() __read_32bit_c0_register($16, 4)
876#define read_c0_config5() __read_32bit_c0_register($16, 5)
877#define read_c0_config6() __read_32bit_c0_register($16, 6)
878#define read_c0_config7() __read_32bit_c0_register($16, 7)
793#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 879#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
794#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 880#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
795#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 881#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
796#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 882#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
883#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
884#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
885#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
886#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
797 887
798/* 888/*
799 * The WatchLo register. There may be upto 8 of them. 889 * The WatchLo register. There may be upto 8 of them.
@@ -917,6 +1007,22 @@ do { \
917#define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1007#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
918#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1008#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
919 1009
1010/* MIPSR2 */
1011#define read_c0_hwrena() __read_32bit_c0_register($7,0)
1012#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1013
1014#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1015#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1016
1017#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1018#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1019
1020#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1021#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1022
1023#define read_c0_ebase() __read_32bit_c0_register($15,1)
1024#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1025
920/* 1026/*
921 * Macros to access the floating point coprocessor control registers 1027 * Macros to access the floating point coprocessor control registers
922 */ 1028 */
@@ -930,6 +1036,284 @@ do { \
930 : "=r" (__res)); \ 1036 : "=r" (__res)); \
931 __res;}) 1037 __res;})
932 1038
1039#define rddsp(mask) \
1040({ \
1041 unsigned int __res; \
1042 \
1043 __asm__ __volatile__( \
1044 " .set push \n" \
1045 " .set noat \n" \
1046 " # rddsp $1, %x1 \n" \
1047 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1048 " move %0, $1 \n" \
1049 " .set pop \n" \
1050 : "=r" (__res) \
1051 : "i" (mask)); \
1052 __res; \
1053})
1054
1055#define wrdsp(val, mask) \
1056do { \
1057 __asm__ __volatile__( \
1058 " .set push \n" \
1059 " .set noat \n" \
1060 " move $1, %0 \n" \
1061 " # wrdsp $1, %x1 \n" \
1062 " .word 0x7c2004f8 | (%x1 << 15) \n" \
1063 " .set pop \n" \
1064 : \
1065 : "r" (val), "i" (mask)); \
1066} while (0)
1067
1068#if 0 /* Need DSP ASE capable assembler ... */
1069#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1070#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1071#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1072#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1073
1074#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1075#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1076#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1077#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1078
1079#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1080#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1081#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1082#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1083
1084#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1085#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1086#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1087#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1088
1089#else
1090
1091#define mfhi0() \
1092({ \
1093 unsigned long __treg; \
1094 \
1095 __asm__ __volatile__( \
1096 " .set push \n" \
1097 " .set noat \n" \
1098 " # mfhi %0, $ac0 \n" \
1099 " .word 0x00000810 \n" \
1100 " move %0, $1 \n" \
1101 " .set pop \n" \
1102 : "=r" (__treg)); \
1103 __treg; \
1104})
1105
1106#define mfhi1() \
1107({ \
1108 unsigned long __treg; \
1109 \
1110 __asm__ __volatile__( \
1111 " .set push \n" \
1112 " .set noat \n" \
1113 " # mfhi %0, $ac1 \n" \
1114 " .word 0x00200810 \n" \
1115 " move %0, $1 \n" \
1116 " .set pop \n" \
1117 : "=r" (__treg)); \
1118 __treg; \
1119})
1120
1121#define mfhi2() \
1122({ \
1123 unsigned long __treg; \
1124 \
1125 __asm__ __volatile__( \
1126 " .set push \n" \
1127 " .set noat \n" \
1128 " # mfhi %0, $ac2 \n" \
1129 " .word 0x00400810 \n" \
1130 " move %0, $1 \n" \
1131 " .set pop \n" \
1132 : "=r" (__treg)); \
1133 __treg; \
1134})
1135
1136#define mfhi3() \
1137({ \
1138 unsigned long __treg; \
1139 \
1140 __asm__ __volatile__( \
1141 " .set push \n" \
1142 " .set noat \n" \
1143 " # mfhi %0, $ac3 \n" \
1144 " .word 0x00600810 \n" \
1145 " move %0, $1 \n" \
1146 " .set pop \n" \
1147 : "=r" (__treg)); \
1148 __treg; \
1149})
1150
1151#define mflo0() \
1152({ \
1153 unsigned long __treg; \
1154 \
1155 __asm__ __volatile__( \
1156 " .set push \n" \
1157 " .set noat \n" \
1158 " # mflo %0, $ac0 \n" \
1159 " .word 0x00000812 \n" \
1160 " move %0, $1 \n" \
1161 " .set pop \n" \
1162 : "=r" (__treg)); \
1163 __treg; \
1164})
1165
1166#define mflo1() \
1167({ \
1168 unsigned long __treg; \
1169 \
1170 __asm__ __volatile__( \
1171 " .set push \n" \
1172 " .set noat \n" \
1173 " # mflo %0, $ac1 \n" \
1174 " .word 0x00200812 \n" \
1175 " move %0, $1 \n" \
1176 " .set pop \n" \
1177 : "=r" (__treg)); \
1178 __treg; \
1179})
1180
1181#define mflo2() \
1182({ \
1183 unsigned long __treg; \
1184 \
1185 __asm__ __volatile__( \
1186 " .set push \n" \
1187 " .set noat \n" \
1188 " # mflo %0, $ac2 \n" \
1189 " .word 0x00400812 \n" \
1190 " move %0, $1 \n" \
1191 " .set pop \n" \
1192 : "=r" (__treg)); \
1193 __treg; \
1194})
1195
1196#define mflo3() \
1197({ \
1198 unsigned long __treg; \
1199 \
1200 __asm__ __volatile__( \
1201 " .set push \n" \
1202 " .set noat \n" \
1203 " # mflo %0, $ac3 \n" \
1204 " .word 0x00600812 \n" \
1205 " move %0, $1 \n" \
1206 " .set pop \n" \
1207 : "=r" (__treg)); \
1208 __treg; \
1209})
1210
1211#define mthi0(x) \
1212do { \
1213 __asm__ __volatile__( \
1214 " .set push \n" \
1215 " .set noat \n" \
1216 " move $1, %0 \n" \
1217 " # mthi $1, $ac0 \n" \
1218 " .word 0x00200011 \n" \
1219 " .set pop \n" \
1220 : \
1221 : "r" (x)); \
1222} while (0)
1223
1224#define mthi1(x) \
1225do { \
1226 __asm__ __volatile__( \
1227 " .set push \n" \
1228 " .set noat \n" \
1229 " move $1, %0 \n" \
1230 " # mthi $1, $ac1 \n" \
1231 " .word 0x00200811 \n" \
1232 " .set pop \n" \
1233 : \
1234 : "r" (x)); \
1235} while (0)
1236
1237#define mthi2(x) \
1238do { \
1239 __asm__ __volatile__( \
1240 " .set push \n" \
1241 " .set noat \n" \
1242 " move $1, %0 \n" \
1243 " # mthi $1, $ac2 \n" \
1244 " .word 0x00201011 \n" \
1245 " .set pop \n" \
1246 : \
1247 : "r" (x)); \
1248} while (0)
1249
1250#define mthi3(x) \
1251do { \
1252 __asm__ __volatile__( \
1253 " .set push \n" \
1254 " .set noat \n" \
1255 " move $1, %0 \n" \
1256 " # mthi $1, $ac3 \n" \
1257 " .word 0x00201811 \n" \
1258 " .set pop \n" \
1259 : \
1260 : "r" (x)); \
1261} while (0)
1262
1263#define mtlo0(x) \
1264do { \
1265 __asm__ __volatile__( \
1266 " .set push \n" \
1267 " .set noat \n" \
1268 " move $1, %0 \n" \
1269 " # mtlo $1, $ac0 \n" \
1270 " .word 0x00200013 \n" \
1271 " .set pop \n" \
1272 : \
1273 : "r" (x)); \
1274} while (0)
1275
1276#define mtlo1(x) \
1277do { \
1278 __asm__ __volatile__( \
1279 " .set push \n" \
1280 " .set noat \n" \
1281 " move $1, %0 \n" \
1282 " # mtlo $1, $ac1 \n" \
1283 " .word 0x00200813 \n" \
1284 " .set pop \n" \
1285 : \
1286 : "r" (x)); \
1287} while (0)
1288
1289#define mtlo2(x) \
1290do { \
1291 __asm__ __volatile__( \
1292 " .set push \n" \
1293 " .set noat \n" \
1294 " move $1, %0 \n" \
1295 " # mtlo $1, $ac2 \n" \
1296 " .word 0x00201013 \n" \
1297 " .set pop \n" \
1298 : \
1299 : "r" (x)); \
1300} while (0)
1301
1302#define mtlo3(x) \
1303do { \
1304 __asm__ __volatile__( \
1305 " .set push \n" \
1306 " .set noat \n" \
1307 " move $1, %0 \n" \
1308 " # mtlo $1, $ac3 \n" \
1309 " .word 0x00201813 \n" \
1310 " .set pop \n" \
1311 : \
1312 : "r" (x)); \
1313} while (0)
1314
1315#endif
1316
933/* 1317/*
934 * TLB operations. 1318 * TLB operations.
935 * 1319 *
@@ -1012,6 +1396,8 @@ __BUILD_SET_C0(status)
1012__BUILD_SET_C0(cause) 1396__BUILD_SET_C0(cause)
1013__BUILD_SET_C0(config) 1397__BUILD_SET_C0(config)
1014__BUILD_SET_C0(intcontrol) 1398__BUILD_SET_C0(intcontrol)
1399__BUILD_SET_C0(intctl)
1400__BUILD_SET_C0(srsmap)
1015 1401
1016#endif /* !__ASSEMBLY__ */ 1402#endif /* !__ASSEMBLY__ */
1017 1403
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-02 10:30:48 -0500