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-rw-r--r--include/asm-mips/mips-boards/generic.h7
-rw-r--r--include/asm-mips/mips-boards/maltaint.h58
-rw-r--r--include/asm-mips/mips-boards/msc01_pci.h241
-rw-r--r--include/asm-mips/mips-boards/sim.h40
-rw-r--r--include/asm-mips/mips-boards/simint.h34
5 files changed, 258 insertions, 122 deletions
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index 65d1d16eab16..25b6ffc26623 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -66,6 +66,7 @@
66#define MIPS_REVISION_CORID_CORE_EMUL 6 66#define MIPS_REVISION_CORID_CORE_EMUL 6
67#define MIPS_REVISION_CORID_CORE_FPGA2 7 67#define MIPS_REVISION_CORID_CORE_FPGA2 7
68#define MIPS_REVISION_CORID_CORE_FPGAR2 8 68#define MIPS_REVISION_CORID_CORE_FPGAR2 8
69#define MIPS_REVISION_CORID_CORE_FPGA3 9
69 70
70/**** Artificial corid defines ****/ 71/**** Artificial corid defines ****/
71/* 72/*
@@ -79,4 +80,10 @@
79 80
80extern unsigned int mips_revision_corid; 81extern unsigned int mips_revision_corid;
81 82
83#ifdef CONFIG_PCI
84extern void mips_pcibios_init(void);
85#else
86#define mips_pcibios_init() do { } while (0)
87#endif
88
82#endif /* __ASM_MIPS_BOARDS_GENERIC_H */ 89#endif /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
index 376181882e81..da6cc2fbbc78 100644
--- a/include/asm-mips/mips-boards/maltaint.h
+++ b/include/asm-mips/mips-boards/maltaint.h
@@ -25,9 +25,63 @@
25#ifndef _MIPS_MALTAINT_H 25#ifndef _MIPS_MALTAINT_H
26#define _MIPS_MALTAINT_H 26#define _MIPS_MALTAINT_H
27 27
28/* Number of IRQ supported on hw interrupt 0. */ 28/*
29#define MALTAINT_END 16 29 * Interrupts 0..15 are used for Malta ISA compatible interrupts
30 */
31#define MALTA_INT_BASE 0
32
33/*
34 * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode)
35 */
36#define MIPSCPU_INT_BASE 16
37
38/* CPU interrupt offsets */
39#define MIPSCPU_INT_SW0 0
40#define MIPSCPU_INT_SW1 1
41#define MIPSCPU_INT_MB0 2
42#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0
43#define MIPSCPU_INT_MB1 3
44#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1
45#define MIPSCPU_INT_MB2 4
46#define MIPSCPU_INT_MB3 5
47#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
48#define MIPSCPU_INT_MB4 6
49#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4
50#define MIPSCPU_INT_CPUCTR 7
51
52/*
53 * Interrupts 64..127 are used for Soc-it Classic interrupts
54 */
55#define MSC01C_INT_BASE 64
56
57/* SOC-it Classic interrupt offsets */
58#define MSC01C_INT_TMR 0
59#define MSC01C_INT_PCI 1
60
61/*
62 * Interrupts 64..127 are used for Soc-it EIC interrupts
63 */
64#define MSC01E_INT_BASE 64
65
66/* SOC-it EIC interrupt offsets */
67#define MSC01E_INT_SW0 1
68#define MSC01E_INT_SW1 2
69#define MSC01E_INT_MB0 3
70#define MSC01E_INT_I8259A MSC01E_INT_MB0
71#define MSC01E_INT_MB1 4
72#define MSC01E_INT_SMI MSC01E_INT_MB1
73#define MSC01E_INT_MB2 5
74#define MSC01E_INT_MB3 6
75#define MSC01E_INT_COREHI MSC01E_INT_MB3
76#define MSC01E_INT_MB4 7
77#define MSC01E_INT_CORELO MSC01E_INT_MB4
78#define MSC01E_INT_TMR 8
79#define MSC01E_INT_PCI 9
80#define MSC01E_INT_PERFCTR 10
81#define MSC01E_INT_CPUCTR 11
30 82
83#ifndef __ASSEMBLY__
31extern void maltaint_init(void); 84extern void maltaint_init(void);
85#endif
32 86
33#endif /* !(_MIPS_MALTAINT_H) */ 87#endif /* !(_MIPS_MALTAINT_H) */
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h
index 6b2a87a38f4b..8eaefb837b9d 100644
--- a/include/asm-mips/mips-boards/msc01_pci.h
+++ b/include/asm-mips/mips-boards/msc01_pci.h
@@ -1,8 +1,9 @@
1/* 1/*
2 * PCI Register definitions for the MIPS System Controller. 2 * PCI Register definitions for the MIPS System Controller.
3 * 3 *
4 * Carsten Langgaard, carstenl@mips.com 4 * Copyright (C) 2002, 2005 MIPS Technologies, Inc. All rights reserved.
5 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. 5 * Authors: Carsten Langgaard <carstenl@mips.com>
6 * Maciej W. Rozycki <macro@mips.com>
6 * 7 *
7 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -29,22 +30,22 @@
29#define MSC01_PCI_CFGADDR_OFS 0x0610 30#define MSC01_PCI_CFGADDR_OFS 0x0610
30#define MSC01_PCI_CFGDATA_OFS 0x0618 31#define MSC01_PCI_CFGDATA_OFS 0x0618
31#define MSC01_PCI_IACK_OFS 0x0620 32#define MSC01_PCI_IACK_OFS 0x0620
32#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */ 33#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */
33#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */ 34#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */
34#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */ 35#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */
35#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */ 36#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */
36#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */ 37#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */
37#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */ 38#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */
38#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */ 39#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */
39#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */ 40#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */
40#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */ 41#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */
41#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */ 42#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */
42#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */ 43#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */
43#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */ 44#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */
44#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */ 45#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */
45#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */ 46#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */
46#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */ 47#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */
47#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */ 48#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */
48#define MSC01_PCI_BAR0_OFS 0x2220 49#define MSC01_PCI_BAR0_OFS 0x2220
49#define MSC01_PCI_CFG_OFS 0x2380 50#define MSC01_PCI_CFG_OFS 0x2380
50#define MSC01_PCI_SWAP_OFS 0x2388 51#define MSC01_PCI_SWAP_OFS 0x2388
@@ -86,73 +87,73 @@
86#define MSC01_PCI_P2SCMAPL_MAP_SHF 24 87#define MSC01_PCI_P2SCMAPL_MAP_SHF 24
87#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000 88#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000
88 89
89#define MSC01_PCI_INTCFG_RST_SHF 10 90#define MSC01_PCI_INTCFG_RST_SHF 10
90#define MSC01_PCI_INTCFG_RST_MSK 0x00000400 91#define MSC01_PCI_INTCFG_RST_MSK 0x00000400
91#define MSC01_PCI_INTCFG_RST_BIT 0x00000400 92#define MSC01_PCI_INTCFG_RST_BIT 0x00000400
92#define MSC01_PCI_INTCFG_MWE_SHF 9 93#define MSC01_PCI_INTCFG_MWE_SHF 9
93#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200 94#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200
94#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200 95#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200
95#define MSC01_PCI_INTCFG_DTO_SHF 8 96#define MSC01_PCI_INTCFG_DTO_SHF 8
96#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100 97#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100
97#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100 98#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100
98#define MSC01_PCI_INTCFG_MA_SHF 7 99#define MSC01_PCI_INTCFG_MA_SHF 7
99#define MSC01_PCI_INTCFG_MA_MSK 0x00000080 100#define MSC01_PCI_INTCFG_MA_MSK 0x00000080
100#define MSC01_PCI_INTCFG_MA_BIT 0x00000080 101#define MSC01_PCI_INTCFG_MA_BIT 0x00000080
101#define MSC01_PCI_INTCFG_TA_SHF 6 102#define MSC01_PCI_INTCFG_TA_SHF 6
102#define MSC01_PCI_INTCFG_TA_MSK 0x00000040 103#define MSC01_PCI_INTCFG_TA_MSK 0x00000040
103#define MSC01_PCI_INTCFG_TA_BIT 0x00000040 104#define MSC01_PCI_INTCFG_TA_BIT 0x00000040
104#define MSC01_PCI_INTCFG_RTY_SHF 5 105#define MSC01_PCI_INTCFG_RTY_SHF 5
105#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020 106#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020
106#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020 107#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020
107#define MSC01_PCI_INTCFG_MWP_SHF 4 108#define MSC01_PCI_INTCFG_MWP_SHF 4
108#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010 109#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010
109#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010 110#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010
110#define MSC01_PCI_INTCFG_MRP_SHF 3 111#define MSC01_PCI_INTCFG_MRP_SHF 3
111#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008 112#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008
112#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008 113#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008
113#define MSC01_PCI_INTCFG_SWP_SHF 2 114#define MSC01_PCI_INTCFG_SWP_SHF 2
114#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004 115#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004
115#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004 116#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004
116#define MSC01_PCI_INTCFG_SRP_SHF 1 117#define MSC01_PCI_INTCFG_SRP_SHF 1
117#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002 118#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002
118#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002 119#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002
119#define MSC01_PCI_INTCFG_SE_SHF 0 120#define MSC01_PCI_INTCFG_SE_SHF 0
120#define MSC01_PCI_INTCFG_SE_MSK 0x00000001 121#define MSC01_PCI_INTCFG_SE_MSK 0x00000001
121#define MSC01_PCI_INTCFG_SE_BIT 0x00000001 122#define MSC01_PCI_INTCFG_SE_BIT 0x00000001
122 123
123#define MSC01_PCI_INTSTAT_RST_SHF 10 124#define MSC01_PCI_INTSTAT_RST_SHF 10
124#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400 125#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400
125#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400 126#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400
126#define MSC01_PCI_INTSTAT_MWE_SHF 9 127#define MSC01_PCI_INTSTAT_MWE_SHF 9
127#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200 128#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200
128#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200 129#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200
129#define MSC01_PCI_INTSTAT_DTO_SHF 8 130#define MSC01_PCI_INTSTAT_DTO_SHF 8
130#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100 131#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100
131#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100 132#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100
132#define MSC01_PCI_INTSTAT_MA_SHF 7 133#define MSC01_PCI_INTSTAT_MA_SHF 7
133#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080 134#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080
134#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080 135#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080
135#define MSC01_PCI_INTSTAT_TA_SHF 6 136#define MSC01_PCI_INTSTAT_TA_SHF 6
136#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040 137#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040
137#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040 138#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040
138#define MSC01_PCI_INTSTAT_RTY_SHF 5 139#define MSC01_PCI_INTSTAT_RTY_SHF 5
139#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020 140#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020
140#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020 141#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020
141#define MSC01_PCI_INTSTAT_MWP_SHF 4 142#define MSC01_PCI_INTSTAT_MWP_SHF 4
142#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010 143#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010
143#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010 144#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010
144#define MSC01_PCI_INTSTAT_MRP_SHF 3 145#define MSC01_PCI_INTSTAT_MRP_SHF 3
145#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008 146#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008
146#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008 147#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008
147#define MSC01_PCI_INTSTAT_SWP_SHF 2 148#define MSC01_PCI_INTSTAT_SWP_SHF 2
148#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004 149#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004
149#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004 150#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004
150#define MSC01_PCI_INTSTAT_SRP_SHF 1 151#define MSC01_PCI_INTSTAT_SRP_SHF 1
151#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002 152#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002
152#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002 153#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002
153#define MSC01_PCI_INTSTAT_SE_SHF 0 154#define MSC01_PCI_INTSTAT_SE_SHF 0
154#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001 155#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001
155#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001 156#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001
156 157
157#define MSC01_PCI_CFGADDR_BNUM_SHF 16 158#define MSC01_PCI_CFGADDR_BNUM_SHF 16
158#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000 159#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000
@@ -167,29 +168,29 @@
167#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff 168#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff
168 169
169/* The defines below are ONLY valid for a MEM bar! */ 170/* The defines below are ONLY valid for a MEM bar! */
170#define MSC01_PCI_BAR0_SIZE_SHF 4 171#define MSC01_PCI_BAR0_SIZE_SHF 4
171#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0 172#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0
172#define MSC01_PCI_BAR0_P_SHF 3 173#define MSC01_PCI_BAR0_P_SHF 3
173#define MSC01_PCI_BAR0_P_MSK 0x00000008 174#define MSC01_PCI_BAR0_P_MSK 0x00000008
174#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK 175#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK
175#define MSC01_PCI_BAR0_D_SHF 1 176#define MSC01_PCI_BAR0_D_SHF 1
176#define MSC01_PCI_BAR0_D_MSK 0x00000006 177#define MSC01_PCI_BAR0_D_MSK 0x00000006
177#define MSC01_PCI_BAR0_T_SHF 0 178#define MSC01_PCI_BAR0_T_SHF 0
178#define MSC01_PCI_BAR0_T_MSK 0x00000001 179#define MSC01_PCI_BAR0_T_MSK 0x00000001
179#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK 180#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK
180 181
181 182
182#define MSC01_PCI_CFG_RA_SHF 17 183#define MSC01_PCI_CFG_RA_SHF 17
183#define MSC01_PCI_CFG_RA_MSK 0x00020000 184#define MSC01_PCI_CFG_RA_MSK 0x00020000
184#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK 185#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK
185#define MSC01_PCI_CFG_G_SHF 16 186#define MSC01_PCI_CFG_G_SHF 16
186#define MSC01_PCI_CFG_G_MSK 0x00010000 187#define MSC01_PCI_CFG_G_MSK 0x00010000
187#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK 188#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK
188#define MSC01_PCI_CFG_EN_SHF 15 189#define MSC01_PCI_CFG_EN_SHF 15
189#define MSC01_PCI_CFG_EN_MSK 0x00008000 190#define MSC01_PCI_CFG_EN_MSK 0x00008000
190#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK 191#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK
191#define MSC01_PCI_CFG_MAXRTRY_SHF 0 192#define MSC01_PCI_CFG_MAXRTRY_SHF 0
192#define MSC01_PCI_CFG_MAXRTRY_MSK 0x000000ff 193#define MSC01_PCI_CFG_MAXRTRY_MSK 0x00000fff
193 194
194#define MSC01_PCI_SWAP_IO_SHF 18 195#define MSC01_PCI_SWAP_IO_SHF 18
195#define MSC01_PCI_SWAP_IO_MSK 0x000c0000 196#define MSC01_PCI_SWAP_IO_MSK 0x000c0000
@@ -206,7 +207,7 @@
206 * FIXME - are these macros specific to Malta and co or to the MSC? If the 207 * FIXME - are these macros specific to Malta and co or to the MSC? If the
207 * latter, they should be moved elsewhere. 208 * latter, they should be moved elsewhere.
208 */ 209 */
209#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 210#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000
210 211
211extern unsigned long _pcictrl_msc; 212extern unsigned long _pcictrl_msc;
212 213
@@ -219,19 +220,19 @@ extern unsigned long _pcictrl_msc;
219 * Registers absolute addresses 220 * Registers absolute addresses
220 */ 221 */
221 222
222#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS) 223#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
223#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS) 224#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
224#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS) 225#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
225#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS) 226#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
226#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS) 227#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
227#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS) 228#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
228#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS) 229#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
229#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS) 230#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
230#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS) 231#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
231#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS) 232#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
232#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS) 233#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
233#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS) 234#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
234#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS) 235#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
235#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS) 236#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
236#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS) 237#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
237#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS) 238#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
@@ -248,7 +249,7 @@ extern unsigned long _pcictrl_msc;
248#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 249#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
249#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 250#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
250#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 251#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
251#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 252#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
252#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS) 253#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
253#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS) 254#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
254#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS) 255#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
diff --git a/include/asm-mips/mips-boards/sim.h b/include/asm-mips/mips-boards/sim.h
new file mode 100644
index 000000000000..acb7c2331d98
--- /dev/null
+++ b/include/asm-mips/mips-boards/sim.h
@@ -0,0 +1,40 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18
19#ifndef _ASM_MIPS_BOARDS_SIM_H
20#define _ASM_MIPS_BOARDS_SIM_H
21
22#define STATS_ON 1
23#define STATS_OFF 2
24#define STATS_CLEAR 3
25#define STATS_DUMP 4
26#define TRACE_ON 5
27#define TRACE_OFF 6
28
29
30#define simcfg(code) \
31({ \
32 __asm__ __volatile__( \
33 "sltiu $0,$0, %0" \
34 ::"i"(code) \
35 ); \
36})
37
38
39
40#endif
diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h
new file mode 100644
index 000000000000..4952e0b3bf11
--- /dev/null
+++ b/include/asm-mips/mips-boards/simint.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 */
17#ifndef _MIPS_SIMINT_H
18#define _MIPS_SIMINT_H
19
20
21#define SIM_INT_BASE 0
22#define MIPSCPU_INT_MB0 2
23#define MIPSCPU_INT_BASE 16
24#define MIPS_CPU_TIMER_IRQ 7
25
26
27#define MIPSCPU_INT_CPUCTR 7
28
29#define MSC01E_INT_BASE 64
30
31#define MIPSCPU_INT_CPUCTR 7
32#define MSC01E_INT_CPUCTR 11
33
34#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-05 02:20:51 -0500