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Diffstat (limited to 'include/asm-mips/mips-boards/generic.h')
| -rw-r--r-- | include/asm-mips/mips-boards/generic.h | 104 |
1 files changed, 0 insertions, 104 deletions
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h deleted file mode 100644 index 7f0b034dd9a5..000000000000 --- a/include/asm-mips/mips-boards/generic.h +++ /dev/null | |||
| @@ -1,104 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Carsten Langgaard, carstenl@mips.com | ||
| 3 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can distribute it and/or modify it | ||
| 6 | * under the terms of the GNU General Public License (Version 2) as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
| 12 | * for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | ||
| 17 | * | ||
| 18 | * Defines of the MIPS boards specific address-MAP, registers, etc. | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_MIPS_BOARDS_GENERIC_H | ||
| 21 | #define __ASM_MIPS_BOARDS_GENERIC_H | ||
| 22 | |||
| 23 | #include <asm/addrspace.h> | ||
| 24 | #include <asm/byteorder.h> | ||
| 25 | #include <asm/mips-boards/bonito64.h> | ||
| 26 | |||
| 27 | /* | ||
| 28 | * Display register base. | ||
| 29 | */ | ||
| 30 | #define ASCII_DISPLAY_WORD_BASE 0x1f000410 | ||
| 31 | #define ASCII_DISPLAY_POS_BASE 0x1f000418 | ||
| 32 | |||
| 33 | |||
| 34 | /* | ||
| 35 | * Yamon Prom print address. | ||
| 36 | */ | ||
| 37 | #define YAMON_PROM_PRINT_ADDR 0x1fc00504 | ||
| 38 | |||
| 39 | |||
| 40 | /* | ||
| 41 | * Reset register. | ||
| 42 | */ | ||
| 43 | #define SOFTRES_REG 0x1f000500 | ||
| 44 | #define GORESET 0x42 | ||
| 45 | |||
| 46 | /* | ||
| 47 | * Revision register. | ||
| 48 | */ | ||
| 49 | #define MIPS_REVISION_REG 0x1fc00010 | ||
| 50 | #define MIPS_REVISION_CORID_QED_RM5261 0 | ||
| 51 | #define MIPS_REVISION_CORID_CORE_LV 1 | ||
| 52 | #define MIPS_REVISION_CORID_BONITO64 2 | ||
| 53 | #define MIPS_REVISION_CORID_CORE_20K 3 | ||
| 54 | #define MIPS_REVISION_CORID_CORE_FPGA 4 | ||
| 55 | #define MIPS_REVISION_CORID_CORE_MSC 5 | ||
| 56 | #define MIPS_REVISION_CORID_CORE_EMUL 6 | ||
| 57 | #define MIPS_REVISION_CORID_CORE_FPGA2 7 | ||
| 58 | #define MIPS_REVISION_CORID_CORE_FPGAR2 8 | ||
| 59 | #define MIPS_REVISION_CORID_CORE_FPGA3 9 | ||
| 60 | #define MIPS_REVISION_CORID_CORE_24K 10 | ||
| 61 | #define MIPS_REVISION_CORID_CORE_FPGA4 11 | ||
| 62 | #define MIPS_REVISION_CORID_CORE_FPGA5 12 | ||
| 63 | |||
| 64 | /**** Artificial corid defines ****/ | ||
| 65 | /* | ||
| 66 | * CoreEMUL with Bonito System Controller is treated like a Core20K | ||
| 67 | * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC | ||
| 68 | */ | ||
| 69 | #define MIPS_REVISION_CORID_CORE_EMUL_BON -1 | ||
| 70 | #define MIPS_REVISION_CORID_CORE_EMUL_MSC -2 | ||
| 71 | |||
| 72 | #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) | ||
| 73 | |||
| 74 | extern int mips_revision_corid; | ||
| 75 | |||
| 76 | #define MIPS_REVISION_SCON_OTHER 0 | ||
| 77 | #define MIPS_REVISION_SCON_SOCITSC 1 | ||
| 78 | #define MIPS_REVISION_SCON_SOCITSCP 2 | ||
| 79 | |||
| 80 | /* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */ | ||
| 81 | #define MIPS_REVISION_SCON_UNKNOWN -1 | ||
| 82 | #define MIPS_REVISION_SCON_GT64120 -2 | ||
| 83 | #define MIPS_REVISION_SCON_BONITO -3 | ||
| 84 | #define MIPS_REVISION_SCON_BRTL -4 | ||
| 85 | #define MIPS_REVISION_SCON_SOCIT -5 | ||
| 86 | #define MIPS_REVISION_SCON_ROCIT -6 | ||
| 87 | |||
| 88 | #define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff) | ||
| 89 | |||
| 90 | extern int mips_revision_sconid; | ||
| 91 | |||
| 92 | extern void mips_reboot_setup(void); | ||
| 93 | |||
| 94 | #ifdef CONFIG_PCI | ||
| 95 | extern void mips_pcibios_init(void); | ||
| 96 | #else | ||
| 97 | #define mips_pcibios_init() do { } while (0) | ||
| 98 | #endif | ||
| 99 | |||
| 100 | #ifdef CONFIG_KGDB | ||
| 101 | extern void kgdb_config(void); | ||
| 102 | #endif | ||
| 103 | |||
| 104 | #endif /* __ASM_MIPS_BOARDS_GENERIC_H */ | ||