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-rw-r--r--include/asm-mips/mach-rm/cpu-feature-overrides.h43
-rw-r--r--include/asm-mips/mach-rm/mc146818rtc.h21
-rw-r--r--include/asm-mips/mach-rm/war.h29
3 files changed, 0 insertions, 93 deletions
diff --git a/include/asm-mips/mach-rm/cpu-feature-overrides.h b/include/asm-mips/mach-rm/cpu-feature-overrides.h
deleted file mode 100644
index ccf543363537..000000000000
--- a/include/asm-mips/mach-rm/cpu-feature-overrides.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * SNI RM200 C apparently was only shipped with R4600 V2.0 and R5000 processors.
9 */
10#ifndef __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
11#define __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
12
13#include <cpu-feature-overrides.h>
14
15#define cpu_has_tlb 1
16#define cpu_has_4kex 1
17#define cpu_has_4k_cache 1
18#define cpu_has_fpu 1
19#define cpu_has_32fpr 1
20#define cpu_has_counter 1
21#define cpu_has_watch 0
22#define cpu_has_mips16 0
23#define cpu_has_divec 0
24#define cpu_has_cache_cdex_p 1
25#define cpu_has_prefetch 0
26#define cpu_has_mcheck 0
27#define cpu_has_ejtag 0
28#define cpu_has_llsc 1
29#define cpu_has_vtag_icache 0
30#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
31#define cpu_has_ic_fills_f_dc 0
32#define cpu_has_dsp 0
33#define cpu_has_nofpuex 0
34#define cpu_has_64bits 1
35#define cpu_has_mipsmt 0
36#define cpu_has_userlocal 0
37
38#define cpu_has_mips32r1 0
39#define cpu_has_mips32r2 0
40#define cpu_has_mips64r1 0
41#define cpu_has_mips64r2 0
42
43#endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-rm/mc146818rtc.h b/include/asm-mips/mach-rm/mc146818rtc.h
deleted file mode 100644
index 145bce096fe9..000000000000
--- a/include/asm-mips/mach-rm/mc146818rtc.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 by Ralf Baechle
7 *
8 * RTC routines for PC style attached Dallas chip with ARC epoch.
9 */
10#ifndef __ASM_MACH_RM_MC146818RTC_H
11#define __ASM_MACH_RM_MC146818RTC_H
12
13#ifdef CONFIG_CPU_BIG_ENDIAN
14#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
15#else
16#define mc146818_decode_year(year) ((year) + 1980)
17#endif
18
19#include_next <mc146818rtc.h>
20
21#endif /* __ASM_MACH_RM_MC146818RTC_H */
diff --git a/include/asm-mips/mach-rm/war.h b/include/asm-mips/mach-rm/war.h
deleted file mode 100644
index 948d3129a114..000000000000
--- a/include/asm-mips/mach-rm/war.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_RM_WAR_H
9#define __ASM_MIPS_MACH_RM_WAR_H
10
11/*
12 * The RM200C seems to have been shipped only with V2.0 R4600s
13 */
14
15#define R4600_V1_INDEX_ICACHEOP_WAR 0
16#define R4600_V1_HIT_CACHEOP_WAR 0
17#define R4600_V2_HIT_CACHEOP_WAR 1
18#define R5432_CP0_INTERRUPT_WAR 0
19#define BCM1250_M3_WAR 0
20#define SIBYTE_1956_WAR 0
21#define MIPS4K_ICACHE_REFILL_WAR 0
22#define MIPS_CACHE_SYNC_WAR 0
23#define TX49XX_ICACHE_INDEX_INV_WAR 0
24#define RM9000_CDEX_SMP_WAR 0
25#define ICACHE_REFILLS_WORKAROUND_WAR 0
26#define R10000_LLSC_WAR 0
27#define MIPS34K_MISSED_ITLB_WAR 0
28
29#endif /* __ASM_MIPS_MACH_RM_WAR_H */