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diff --git a/include/asm-mips/mach-rc32434/pci.h b/include/asm-mips/mach-rc32434/pci.h
deleted file mode 100644
index 410638f2af74..000000000000
--- a/include/asm-mips/mach-rc32434/pci.h
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1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Copyright 2004 IDT Inc. (rischelp@idt.com)
23 *
24 * Initial Release
25 */
26
27#ifndef _ASM_RC32434_PCI_H_
28#define _ASM_RC32434_PCI_H_
29
30#define epld_mask ((volatile unsigned char *)0xB900000d)
31
32#define PCI0_BASE_ADDR 0x18080000
33#define PCI_LBA_COUNT 4
34
35struct pci_map {
36 u32 address; /* Address. */
37 u32 control; /* Control. */
38 u32 mapping; /* mapping. */
39};
40
41struct pci_reg {
42 u32 pcic;
43 u32 pcis;
44 u32 pcism;
45 u32 pcicfga;
46 u32 pcicfgd;
47 volatile struct pci_map pcilba[PCI_LBA_COUNT];
48 u32 pcidac;
49 u32 pcidas;
50 u32 pcidasm;
51 u32 pcidad;
52 u32 pcidma8c;
53 u32 pcidma9c;
54 u32 pcitc;
55};
56
57#define PCI_MSU_COUNT 2
58
59struct pci_msu {
60 u32 pciim[PCI_MSU_COUNT];
61 u32 pciom[PCI_MSU_COUNT];
62 u32 pciid;
63 u32 pciiic;
64 u32 pciiim;
65 u32 pciiod;
66 u32 pciioic;
67 u32 pciioim;
68};
69
70/*
71 * PCI Control Register
72 */
73
74#define PCI_CTL_EN (1 << 0)
75#define PCI_CTL_TNR (1 << 1)
76#define PCI_CTL_SCE (1 << 2)
77#define PCI_CTL_IEN (1 << 3)
78#define PCI_CTL_AAA (1 << 4)
79#define PCI_CTL_EAP (1 << 5)
80#define PCI_CTL_PCIM_BIT 6
81#define PCI_CTL_PCIM 0x000001c0
82
83#define PCI_CTL_PCIM_DIS 0
84#define PCI_CTL_PCIM_TNR 1 /* Satellite - target not ready */
85#define PCI_CTL_PCIM_SUS 2 /* Satellite - suspended CPU. */
86#define PCI_CTL_PCIM_EXT 3 /* Host - external arbiter. */
87#define PCI_CTL PCIM_PRIO 4 /* Host - fixed priority arb. */
88#define PCI_CTL_PCIM_RR 5 /* Host - round robin priority. */
89#define PCI_CTL_PCIM_RSVD6 6
90#define PCI_CTL_PCIM_RSVD7 7
91
92#define PCI_CTL_IGM (1 << 9)
93
94/*
95 * PCI Status Register
96 */
97
98#define PCI_STAT_EED (1 << 0)
99#define PCI_STAT_WR (1 << 1)
100#define PCI_STAT_NMI (1 << 2)
101#define PCI_STAT_II (1 << 3)
102#define PCI_STAT_CWE (1 << 4)
103#define PCI_STAT_CRE (1 << 5)
104#define PCI_STAT_MDPE (1 << 6)
105#define PCI_STAT_STA (1 << 7)
106#define PCI_STAT_RTA (1 << 8)
107#define PCI_STAT_RMA (1 << 9)
108#define PCI_STAT_SSE (1 << 10)
109#define PCI_STAT_OSE (1 << 11)
110#define PCI_STAT_PE (1 << 12)
111#define PCI_STAT_TAE (1 << 13)
112#define PCI_STAT_RLE (1 << 14)
113#define PCI_STAT_BME (1 << 15)
114#define PCI_STAT_PRD (1 << 16)
115#define PCI_STAT_RIP (1 << 17)
116
117/*
118 * PCI Status Mask Register
119 */
120
121#define PCI_STATM_EED PCI_STAT_EED
122#define PCI_STATM_WR PCI_STAT_WR
123#define PCI_STATM_NMI PCI_STAT_NMI
124#define PCI_STATM_II PCI_STAT_II
125#define PCI_STATM_CWE PCI_STAT_CWE
126#define PCI_STATM_CRE PCI_STAT_CRE
127#define PCI_STATM_MDPE PCI_STAT_MDPE
128#define PCI_STATM_STA PCI_STAT_STA
129#define PCI_STATM_RTA PCI_STAT_RTA
130#define PCI_STATM_RMA PCI_STAT_RMA
131#define PCI_STATM_SSE PCI_STAT_SSE
132#define PCI_STATM_OSE PCI_STAT_OSE
133#define PCI_STATM_PE PCI_STAT_PE
134#define PCI_STATM_TAE PCI_STAT_TAE
135#define PCI_STATM_RLE PCI_STAT_RLE
136#define PCI_STATM_BME PCI_STAT_BME
137#define PCI_STATM_PRD PCI_STAT_PRD
138#define PCI_STATM_RIP PCI_STAT_RIP
139
140/*
141 * PCI Configuration Address Register
142 */
143#define PCI_CFGA_REG_BIT 2
144#define PCI_CFGA_REG 0x000000fc
145#define PCI_CFGA_REG_ID (0x00 >> 2) /* use PCFGID */
146#define PCI_CFGA_REG_04 (0x04 >> 2) /* use PCFG04_ */
147#define PCI_CFGA_REG_08 (0x08 >> 2) /* use PCFG08_ */
148#define PCI_CFGA_REG_0C (0x0C >> 2) /* use PCFG0C_ */
149#define PCI_CFGA_REG_PBA0 (0x10 >> 2) /* use PCIPBA_ */
150#define PCI_CFGA_REG_PBA1 (0x14 >> 2) /* use PCIPBA_ */
151#define PCI_CFGA_REG_PBA2 (0x18 >> 2) /* use PCIPBA_ */
152#define PCI_CFGA_REG_PBA3 (0x1c >> 2) /* use PCIPBA_ */
153#define PCI_CFGA_REG_SUBSYS (0x2c >> 2) /* use PCFGSS_ */
154#define PCI_CFGA_REG_3C (0x3C >> 2) /* use PCFG3C_ */
155#define PCI_CFGA_REG_PBBA0C (0x44 >> 2) /* use PCIPBAC_ */
156#define PCI_CFGA_REG_PBA0M (0x48 >> 2)
157#define PCI_CFGA_REG_PBA1C (0x4c >> 2) /* use PCIPBAC_ */
158#define PCI_CFGA_REG_PBA1M (0x50 >> 2)
159#define PCI_CFGA_REG_PBA2C (0x54 >> 2) /* use PCIPBAC_ */
160#define PCI_CFGA_REG_PBA2M (0x58 >> 2)
161#define PCI_CFGA_REG_PBA3C (0x5c >> 2) /* use PCIPBAC_ */
162#define PCI_CFGA_REG_PBA3M (0x60 >> 2)
163#define PCI_CFGA_REG_PMGT (0x64 >> 2)
164#define PCI_CFGA_FUNC_BIT 8
165#define PCI_CFGA_FUNC 0x00000700
166#define PCI_CFGA_DEV_BIT 11
167#define PCI_CFGA_DEV 0x0000f800
168#define PCI_CFGA_DEV_INTERN 0
169#define PCI_CFGA_BUS_BIT 16
170#define PCI CFGA_BUS 0x00ff0000
171#define PCI_CFGA_BUS_TYPE0 0
172#define PCI_CFGA_EN (1 << 31)
173
174/* PCI CFG04 commands */
175#define PCI_CFG04_CMD_IO_ENA (1 << 0)
176#define PCI_CFG04_CMD_MEM_ENA (1 << 1)
177#define PCI_CFG04_CMD_BM_ENA (1 << 2)
178#define PCI_CFG04_CMD_MW_INV (1 << 4)
179#define PCI_CFG04_CMD_PAR_ENA (1 << 6)
180#define PCI_CFG04_CMD_SER_ENA (1 << 8)
181#define PCI_CFG04_CMD_FAST_ENA (1 << 9)
182
183/* PCI CFG04 status fields */
184#define PCI_CFG04_STAT_BIT 16
185#define PCI_CFG04_STAT 0xffff0000
186#define PCI_CFG04_STAT_66_MHZ (1 << 21)
187#define PCI_CFG04_STAT_FBB (1 << 23)
188#define PCI_CFG04_STAT_MDPE (1 << 24)
189#define PCI_CFG04_STAT_DST (1 << 25)
190#define PCI_CFG04_STAT_STA (1 << 27)
191#define PCI_CFG04_STAT_RTA (1 << 28)
192#define PCI_CFG04_STAT_RMA (1 << 29)
193#define PCI_CFG04_STAT_SSE (1 << 30)
194#define PCI_CFG04_STAT_PE (1 << 31)
195
196#define PCI_PBA_MSI (1 << 0)
197#define PCI_PBA_P (1 << 2)
198
199/* PCI PBAC registers */
200#define PCI_PBAC_MSI (1 << 0)
201#define PCI_PBAC_P (1 << 1)
202#define PCI_PBAC_SIZE_BIT 2
203#define PCI_PBAC_SIZE 0x0000007c
204#define PCI_PBAC_SB (1 << 7)
205#define PCI_PBAC_PP (1 << 8)
206#define PCI_PBAC_MR_BIT 9
207#define PCI_PBAC_MR 0x00000600
208#define PCI_PBAC_MR_RD 0
209#define PCI_PBAC_MR_RD_LINE 1
210#define PCI_PBAC_MR_RD_MULT 2
211#define PCI_PBAC_MRL (1 << 11)
212#define PCI_PBAC_MRM (1 << 12)
213#define PCI_PBAC_TRP (1 << 13)
214
215#define PCI_CFG40_TRDY_TIM 0x000000ff
216#define PCI_CFG40_RET_LIM 0x0000ff00
217
218/*
219 * PCI Local Base Address [0|1|2|3] Register
220 */
221
222#define PCI_LBA_BADDR_BIT 0
223#define PCI_LBA_BADDR 0xffffff00
224
225/*
226 * PCI Local Base Address Control Register
227 */
228
229#define PCI_LBAC_MSI (1 << 0)
230#define PCI_LBAC_MSI_MEM 0
231#define PCI_LBAC_MSI_IO 1
232#define PCI_LBAC_SIZE_BIT 2
233#define PCI_LBAC_SIZE 0x0000007c
234#define PCI_LBAC_SB (1 << 7)
235#define PCI_LBAC_RT (1 << 8)
236#define PCI_LBAC_RT_NO_PREF 0
237#define PCI_LBAC_RT_PREF 1
238
239/*
240 * PCI Local Base Address [0|1|2|3] Mapping Register
241 */
242#define PCI_LBAM_MADDR_BIT 8
243#define PCI_LBAM_MADDR 0xffffff00
244
245/*
246 * PCI Decoupled Access Control Register
247 */
248#define PCI_DAC_DEN (1 << 0)
249
250/*
251 * PCI Decoupled Access Status Register
252 */
253#define PCI_DAS_D (1 << 0)
254#define PCI_DAS_B (1 << 1)
255#define PCI_DAS_E (1 << 2)
256#define PCI_DAS_OFE (1 << 3)
257#define PCI_DAS_OFF (1 << 4)
258#define PCI_DAS_IFE (1 << 5)
259#define PCI_DAS_IFF (1 << 6)
260
261/*
262 * PCI DMA Channel 8 Configuration Register
263 */
264#define PCI_DMA8C_MBS_BIT 0
265#define PCI_DMA8C_MBS 0x00000fff /* Maximum Burst Size. */
266#define PCI_DMA8C_OUR (1 << 12)
267
268/*
269 * PCI DMA Channel 9 Configuration Register
270 */
271#define PCI_DMA9C_MBS_BIT 0 /* Maximum Burst Size. */
272#define PCI_DMA9C_MBS 0x00000fff
273
274/*
275 * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
276 */
277
278#define PCI_DMAD_PT_BIT 22 /* in DEVCMD field (descriptor) */
279#define PCI_DMAD_PT 0x00c00000 /* preferred transaction field */
280/* These are for reads (DMA channel 8) */
281#define PCI_DMAD_DEVCMD_MR 0 /* memory read */
282#define PCI_DMAD_DEVCMD_MRL 1 /* memory read line */
283#define PCI_DMAD_DEVCMD_MRM 2 /* memory read multiple */
284#define PCI_DMAD_DEVCMD_IOR 3 /* I/O read */
285/* These are for writes (DMA channel 9) */
286#define PCI_DMAD_DEVCMD_MW 0 /* memory write */
287#define PCI_DMAD_DEVCMD_MWI 1 /* memory write invalidate */
288#define PCI_DMAD_DEVCMD_IOW 3 /* I/O write */
289
290/* Swap byte field applies to both DMA channel 8 and 9 */
291#define PCI_DMAD_SB (1 << 24) /* swap byte field */
292
293
294/*
295 * PCI Target Control Register
296 */
297
298#define PCI_TC_RTIMER_BIT 0
299#define PCI_TC_RTIMER 0x000000ff
300#define PCI_TC_DTIMER_BIT 8
301#define PCI_TC_DTIMER 0x0000ff00
302#define PCI_TC_RDR (1 << 18)
303#define PCI_TC_DDT (1 << 19)
304
305/*
306 * PCI messaging unit [applies to both inbound and outbound registers ]
307 */
308#define PCI_MSU_M0 (1 << 0)
309#define PCI_MSU_M1 (1 << 1)
310#define PCI_MSU_DB (1 << 2)
311
312#define PCI_MSG_ADDR 0xB8088010
313#define PCI0_ADDR 0xB8080000
314#define rc32434_pci ((struct pci_reg *) PCI0_ADDR)
315#define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR)
316
317#define PCIM_SHFT 0x6
318#define PCIM_BIT_LEN 0x7
319#define PCIM_H_EA 0x3
320#define PCIM_H_IA_FIX 0x4
321#define PCIM_H_IA_RR 0x5
322#if 0
323#define PCI_ADDR_START 0x13000000
324#endif
325
326#define PCI_ADDR_START 0x50000000
327
328#define CPUTOPCI_MEM_WIN 0x02000000
329#define CPUTOPCI_IO_WIN 0x00100000
330#define PCILBA_SIZE_SHFT 2
331#define PCILBA_SIZE_MASK 0x1F
332#define SIZE_256MB 0x1C
333#define SIZE_128MB 0x1B
334#define SIZE_64MB 0x1A
335#define SIZE_32MB 0x19
336#define SIZE_16MB 0x18
337#define SIZE_4MB 0x16
338#define SIZE_2MB 0x15
339#define SIZE_1MB 0x14
340#define KORINA_CONFIG0_ADDR 0x80000000
341#define KORINA_CONFIG1_ADDR 0x80000004
342#define KORINA_CONFIG2_ADDR 0x80000008
343#define KORINA_CONFIG3_ADDR 0x8000000C
344#define KORINA_CONFIG4_ADDR 0x80000010
345#define KORINA_CONFIG5_ADDR 0x80000014
346#define KORINA_CONFIG6_ADDR 0x80000018
347#define KORINA_CONFIG7_ADDR 0x8000001C
348#define KORINA_CONFIG8_ADDR 0x80000020
349#define KORINA_CONFIG9_ADDR 0x80000024
350#define KORINA_CONFIG10_ADDR 0x80000028
351#define KORINA_CONFIG11_ADDR 0x8000002C
352#define KORINA_CONFIG12_ADDR 0x80000030
353#define KORINA_CONFIG13_ADDR 0x80000034
354#define KORINA_CONFIG14_ADDR 0x80000038
355#define KORINA_CONFIG15_ADDR 0x8000003C
356#define KORINA_CONFIG16_ADDR 0x80000040
357#define KORINA_CONFIG17_ADDR 0x80000044
358#define KORINA_CONFIG18_ADDR 0x80000048
359#define KORINA_CONFIG19_ADDR 0x8000004C
360#define KORINA_CONFIG20_ADDR 0x80000050
361#define KORINA_CONFIG21_ADDR 0x80000054
362#define KORINA_CONFIG22_ADDR 0x80000058
363#define KORINA_CONFIG23_ADDR 0x8000005C
364#define KORINA_CONFIG24_ADDR 0x80000060
365#define KORINA_CONFIG25_ADDR 0x80000064
366#define KORINA_CMD (PCI_CFG04_CMD_IO_ENA | \
367 PCI_CFG04_CMD_MEM_ENA | \
368 PCI_CFG04_CMD_BM_ENA | \
369 PCI_CFG04_CMD_MW_INV | \
370 PCI_CFG04_CMD_PAR_ENA | \
371 PCI_CFG04_CMD_SER_ENA)
372
373#define KORINA_STAT (PCI_CFG04_STAT_MDPE | \
374 PCI_CFG04_STAT_STA | \
375 PCI_CFG04_STAT_RTA | \
376 PCI_CFG04_STAT_RMA | \
377 PCI_CFG04_STAT_SSE | \
378 PCI_CFG04_STAT_PE)
379
380#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
381
382#define KORINA_REVID 0
383#define KORINA_CLASS_CODE 0
384#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
385 KORINA_REVID)
386
387#define KORINA_CACHE_LINE_SIZE 4
388#define KORINA_MASTER_LAT 0x3c
389#define KORINA_HEADER_TYPE 0
390#define KORINA_BIST 0
391
392#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
393 (KORINA_HEADER_TYPE<<16) | \
394 (KORINA_MASTER_LAT<<8) | \
395 KORINA_CACHE_LINE_SIZE)
396
397#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
398#define KORINA_BAR1 0x18800001 /* 1 MB IO */
399#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
400 internal Registers */
401#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
402
403#define KORINA_CNFG4 KORINA_BAR0
404#define KORINA_CNFG5 KORINA_BAR1
405#define KORINA_CNFG6 KORINA_BAR2
406#define KORINA_CNFG7 KORINA_BAR3
407
408#define KORINA_SUBSYS_VENDOR_ID 0x011d
409#define KORINA_SUBSYSTEM_ID 0x0214
410#define KORINA_CNFG8 0
411#define KORINA_CNFG9 0
412#define KORINA_CNFG10 0
413#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
414 KORINA_SUBSYSTEM_ID)
415#define KORINA_INT_LINE 1
416#define KORINA_INT_PIN 1
417#define KORINA_MIN_GNT 8
418#define KORINA_MAX_LAT 0x38
419#define KORINA_CNFG12 0
420#define KORINA_CNFG13 0
421#define KORINA_CNFG14 0
422#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
423 (KORINA_MIN_GNT<<16) | \
424 (KORINA_INT_PIN<<8) | \
425 KORINA_INT_LINE)
426#define KORINA_RETRY_LIMIT 0x80
427#define KORINA_TRDY_LIMIT 0x80
428#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
429 KORINA_TRDY_LIMIT)
430#define PCI_PBAxC_R 0x0
431#define PCI_PBAxC_RL 0x1
432#define PCI_PBAxC_RM 0x2
433#define SIZE_SHFT 2
434
435#if defined(__MIPSEB__)
436#define KORINA_PBA0C (PCI_PBAC_MRL | PCI_PBAC_SB | \
437 ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
438 PCI_PBAC_PP | \
439 (SIZE_128MB<<SIZE_SHFT) | \
440 PCI_PBAC_P)
441#else
442#define KORINA_PBA0C (PCI_PBAC_MRL | \
443 ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
444 PCI_PBAC_PP | \
445 (SIZE_128MB<<SIZE_SHFT) | \
446 PCI_PBAC_P)
447#endif
448#define KORINA_CNFG17 KORINA_PBA0C
449#define KORINA_PBA0M 0x0
450#define KORINA_CNFG18 KORINA_PBA0M
451
452#if defined(__MIPSEB__)
453#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCI_PBAC_SB | \
454 PCI_PBAC_MSI)
455#else
456#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
457 PCI_PBAC_MSI)
458#endif
459#define KORINA_CNFG19 KORINA_PBA1C
460#define KORINA_PBA1M 0x0
461#define KORINA_CNFG20 KORINA_PBA1M
462
463#if defined(__MIPSEB__)
464#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCI_PBAC_SB | \
465 PCI_PBAC_MSI)
466#else
467#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
468 PCI_PBAC_MSI)
469#endif
470#define KORINA_CNFG21 KORINA_PBA2C
471#define KORINA_PBA2M 0x18000000
472#define KORINA_CNFG22 KORINA_PBA2M
473#define KORINA_PBA3C 0
474#define KORINA_CNFG23 KORINA_PBA3C
475#define KORINA_PBA3M 0
476#define KORINA_CNFG24 KORINA_PBA3M
477
478#define PCITC_DTIMER_VAL 8
479#define PCITC_RTIMER_VAL 0x10
480
481#endif /* __ASM_RC32434_PCI_H */
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