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-rw-r--r--include/asm-mips/mach-rc32434/gpio.h126
1 files changed, 0 insertions, 126 deletions
diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h
deleted file mode 100644
index f946f5f45bbb..000000000000
--- a/include/asm-mips/mach-rc32434/gpio.h
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * Copyright 2002 Integrated Device Technology, Inc.
3 * All rights reserved.
4 *
5 * GPIO register definition.
6 *
7 * Author : ryan.holmQVist@idt.com
8 * Date : 20011005
9 * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
10 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
11 */
12
13#ifndef _RC32434_GPIO_H_
14#define _RC32434_GPIO_H_
15
16#include <linux/types.h>
17
18struct rb532_gpio_reg {
19 u32 gpiofunc; /* GPIO Function Register
20 * gpiofunc[x]==0 bit = gpio
21 * func[x]==1 bit = altfunc
22 */
23 u32 gpiocfg; /* GPIO Configuration Register
24 * gpiocfg[x]==0 bit = input
25 * gpiocfg[x]==1 bit = output
26 */
27 u32 gpiod; /* GPIO Data Register
28 * gpiod[x] read/write gpio pinX status
29 */
30 u32 gpioilevel; /* GPIO Interrupt Status Register
31 * interrupt level (see gpioistat)
32 */
33 u32 gpioistat; /* Gpio Interrupt Status Register
34 * istat[x] = (gpiod[x] == level[x])
35 * cleared in ISR (STICKY bits)
36 */
37 u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
38};
39
40/* UART GPIO signals */
41#define RC32434_UART0_SOUT (1 << 0)
42#define RC32434_UART0_SIN (1 << 1)
43#define RC32434_UART0_RTS (1 << 2)
44#define RC32434_UART0_CTS (1 << 3)
45
46/* M & P bus GPIO signals */
47#define RC32434_MP_BIT_22 (1 << 4)
48#define RC32434_MP_BIT_23 (1 << 5)
49#define RC32434_MP_BIT_24 (1 << 6)
50#define RC32434_MP_BIT_25 (1 << 7)
51
52/* CPU GPIO signals */
53#define RC32434_CPU_GPIO (1 << 8)
54
55/* Reserved GPIO signals */
56#define RC32434_AF_SPARE_6 (1 << 9)
57#define RC32434_AF_SPARE_4 (1 << 10)
58#define RC32434_AF_SPARE_3 (1 << 11)
59#define RC32434_AF_SPARE_2 (1 << 12)
60
61/* PCI messaging unit */
62#define RC32434_PCI_MSU_GPIO (1 << 13)
63
64
65extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
66extern unsigned get_434_reg(unsigned reg_offs);
67extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
68extern unsigned char get_latch_u5(void);
69
70extern int rb532_gpio_get_value(unsigned gpio);
71extern void rb532_gpio_set_value(unsigned gpio, int value);
72extern int rb532_gpio_direction_input(unsigned gpio);
73extern int rb532_gpio_direction_output(unsigned gpio, int value);
74extern void rb532_gpio_set_int_level(unsigned gpio, int value);
75extern int rb532_gpio_get_int_level(unsigned gpio);
76extern void rb532_gpio_set_int_status(unsigned gpio, int value);
77extern int rb532_gpio_get_int_status(unsigned gpio);
78
79
80/* Wrappers for the arch-neutral GPIO API */
81
82static inline int gpio_request(unsigned gpio, const char *label)
83{
84 /* Not yet implemented */
85 return 0;
86}
87
88static inline void gpio_free(unsigned gpio)
89{
90 /* Not yet implemented */
91}
92
93static inline int gpio_direction_input(unsigned gpio)
94{
95 return rb532_gpio_direction_input(gpio);
96}
97
98static inline int gpio_direction_output(unsigned gpio, int value)
99{
100 return rb532_gpio_direction_output(gpio, value);
101}
102
103static inline int gpio_get_value(unsigned gpio)
104{
105 return rb532_gpio_get_value(gpio);
106}
107
108static inline void gpio_set_value(unsigned gpio, int value)
109{
110 rb532_gpio_set_value(gpio, value);
111}
112
113static inline int gpio_to_irq(unsigned gpio)
114{
115 return gpio;
116}
117
118static inline int irq_to_gpio(unsigned irq)
119{
120 return irq;
121}
122
123/* For cansleep */
124#include <asm-generic/gpio.h>
125
126#endif /* _RC32434_GPIO_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 00:58:35 -0500