2 files changed, 0 insertions, 57 deletions

diff --git a/include/asm-mips/mach-qemu/cpu-feature-overrides.h b/include/asm-mips/mach-qemu/cpu-feature-overrides.h
deleted file mode 100644
index d2daaed235d5..000000000000
--- a/include/asm-mips/mach-qemu/cpu-feature-overrides.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 07 Ralf Baechle
- */
-#ifndef __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
-
-/*
- * QEMU only comes with a hazard-free MIPS32 processor, so things are easy.
- */
-#define cpu_has_mips16          0
-#define cpu_has_divec           0
-#define cpu_has_cache_cdex_p    0
-#define cpu_has_prefetch        0
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-
-#define cpu_has_llsc            1
-#define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      0
-#define cpu_has_ic_fills_f_dc   0
-
-#define cpu_has_dsp             0
-#define cpu_has_mipsmt          0
-
-#define cpu_has_nofpuex         0
-#define cpu_has_64bits          0
-
-#endif /* __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-qemu/war.h b/include/asm-mips/mach-qemu/war.h
deleted file mode 100644
index 0eaf0c548a47..000000000000
--- a/include/asm-mips/mach-qemu/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_QEMU_WAR_H
-#define __ASM_MIPS_MACH_QEMU_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_QEMU_WAR_H */