diff options
Diffstat (limited to 'include/asm-mips/mach-pnx8550/kernel-entry-init.h')
| -rw-r--r-- | include/asm-mips/mach-pnx8550/kernel-entry-init.h | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h index 57102fa9da51..982079f410b5 100644 --- a/include/asm-mips/mach-pnx8550/kernel-entry-init.h +++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h | |||
| @@ -200,10 +200,10 @@ pr4450_instr_cache_invalidated: | |||
| 200 | 200 | ||
| 201 | icache_invd_loop: | 201 | icache_invd_loop: |
| 202 | /* 9 == register t1 */ | 202 | /* 9 == register t1 */ |
| 203 | .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ | 203 | .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ |
| 204 | (0 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY0 */ | 204 | (0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */ |
| 205 | .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ | 205 | .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ |
| 206 | (1 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY1 */ | 206 | (1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */ |
| 207 | 207 | ||
| 208 | addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */ | 208 | addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */ |
| 209 | bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */ | 209 | bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */ |
| @@ -235,14 +235,14 @@ pr4450_instr_cache_invalidated: | |||
| 235 | 235 | ||
| 236 | dcache_wbinvd_loop: | 236 | dcache_wbinvd_loop: |
| 237 | /* 9 == register t1 */ | 237 | /* 9 == register t1 */ |
| 238 | .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ | 238 | .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ |
| 239 | (0 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY0 */ | 239 | (0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */ |
| 240 | .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ | 240 | .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ |
| 241 | (1 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY1 */ | 241 | (1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */ |
| 242 | .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ | 242 | .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ |
| 243 | (2 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY2 */ | 243 | (2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */ |
| 244 | .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ | 244 | .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ |
| 245 | (3 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY3 */ | 245 | (3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */ |
| 246 | 246 | ||
| 247 | addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */ | 247 | addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */ |
| 248 | bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */ | 248 | bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */ |