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-rw-r--r--include/asm-mips/mach-pb1x00/mc146818rtc.h34
-rw-r--r--include/asm-mips/mach-pb1x00/pb1000.h172
-rw-r--r--include/asm-mips/mach-pb1x00/pb1100.h85
-rw-r--r--include/asm-mips/mach-pb1x00/pb1500.h51
-rw-r--r--include/asm-mips/mach-pb1x00/pb1550.h169
5 files changed, 511 insertions, 0 deletions
diff --git a/include/asm-mips/mach-pb1x00/mc146818rtc.h b/include/asm-mips/mach-pb1x00/mc146818rtc.h
new file mode 100644
index 000000000000..622c58710e5b
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/mc146818rtc.h
@@ -0,0 +1,34 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998, 2001, 03 by Ralf Baechle
7 *
8 * RTC routines for PC style attached Dallas chip.
9 */
10#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
11#define __ASM_MACH_AU1XX_MC146818RTC_H
12
13#include <asm/io.h>
14#include <asm/mach-au1x00/au1000.h>
15
16#define RTC_PORT(x) (0x0c000000 + (x))
17#define RTC_IRQ 8
18#define PB1500_RTC_ADDR 0x0c000000
19
20static inline unsigned char CMOS_READ(unsigned long offset)
21{
22 offset <<= 2;
23 return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
24}
25
26static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
27{
28 offset <<= 2;
29 au_writel(data, offset + PB1500_RTC_ADDR);
30}
31
32#define RTC_ALWAYS_BCD 1
33
34#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h
new file mode 100644
index 000000000000..50c1e413a688
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/pb1000.h
@@ -0,0 +1,172 @@
1/*
2 * Alchemy Semi PB1000 Referrence Board
3 *
4 * Copyright 2001 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc.
6 * ppopov@mvista.com or source@mvista.com
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_PB1000_H
28#define __ASM_PB1000_H
29
30/* PCMCIA PB1000 specific defines */
31#define PCMCIA_MAX_SOCK 1
32#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
33
34#define PB1000_PCR 0xBE000000
35 #define PCR_SLOT_0_VPP0 (1<<0)
36 #define PCR_SLOT_0_VPP1 (1<<1)
37 #define PCR_SLOT_0_VCC0 (1<<2)
38 #define PCR_SLOT_0_VCC1 (1<<3)
39 #define PCR_SLOT_0_RST (1<<4)
40
41 #define PCR_SLOT_1_VPP0 (1<<8)
42 #define PCR_SLOT_1_VPP1 (1<<9)
43 #define PCR_SLOT_1_VCC0 (1<<10)
44 #define PCR_SLOT_1_VCC1 (1<<11)
45 #define PCR_SLOT_1_RST (1<<12)
46
47#define PB1000_MDR 0xBE000004
48 #define MDR_PI (1<<5) /* pcmcia int latch */
49 #define MDR_EPI (1<<14) /* enable pcmcia int */
50 #define MDR_CPI (1<<15) /* clear pcmcia int */
51
52#define PB1000_ACR1 0xBE000008
53 #define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */
54 #define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */
55 #define ACR1_SLOT_0_READY (1<<2) /* ready */
56 #define ACR1_SLOT_0_STATUS (1<<3) /* status change */
57 #define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */
58 #define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */
59 #define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */
60 #define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */
61 #define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */
62 #define ACR1_SLOT_1_READY (1<<10) /* ready */
63 #define ACR1_SLOT_1_STATUS (1<<11) /* status change */
64 #define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */
65 #define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */
66 #define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */
67
68#define CPLD_AUX0 0xBE00000C
69#define CPLD_AUX1 0xBE000010
70#define CPLD_AUX2 0xBE000014
71
72/* Voltage levels */
73
74/* VPPEN1 - VPPEN0 */
75#define VPP_GND ((0<<1) | (0<<0))
76#define VPP_5V ((1<<1) | (0<<0))
77#define VPP_3V ((0<<1) | (1<<0))
78#define VPP_12V ((0<<1) | (1<<0))
79#define VPP_HIZ ((1<<1) | (1<<0))
80
81/* VCCEN1 - VCCEN0 */
82#define VCC_3V ((0<<1) | (1<<0))
83#define VCC_5V ((1<<1) | (0<<0))
84#define VCC_HIZ ((0<<1) | (0<<0))
85
86/* VPP/VCC */
87#define SET_VCC_VPP(VCC, VPP, SLOT)\
88 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
89
90
91/* PCI PB1000 specific defines */
92/* The reason these defines are here instead of au1000.h is because
93 * the Au1000 does not have a PCI bus controller so the PCI implementation
94 * on the some of the older Pb1000 boards was very board specific.
95 */
96#define PCI_CONFIG_BASE 0xBA020000 /* the only external slot */
97
98#define SDRAM_DEVID 0xBA010000
99#define SDRAM_CMD 0xBA010004
100#define SDRAM_CLASS 0xBA010008
101#define SDRAM_MISC 0xBA01000C
102#define SDRAM_MBAR 0xBA010010
103
104#define PCI_IO_DATA_PORT 0xBA800000
105
106#define PCI_IO_ADDR 0xBE00001C
107#define PCI_INT_ACK 0xBBC00000
108#define PCI_IO_READ 0xBBC00020
109#define PCI_IO_WRITE 0xBBC00030
110
111#define PCI_BRIDGE_CONFIG 0xBE000018
112
113#define PCI_IO_START 0x10000000
114#define PCI_IO_END 0x1000ffff
115#define PCI_MEM_START 0x18000000
116#define PCI_MEM_END 0x18ffffff
117
118#define PCI_FIRST_DEVFN 0
119#define PCI_LAST_DEVFN 1
120
121static inline u8 au_pci_io_readb(u32 addr)
122{
123 writel(addr, PCI_IO_ADDR);
124 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
125 return (readl(PCI_IO_DATA_PORT) & 0xff);
126}
127
128static inline u16 au_pci_io_readw(u32 addr)
129{
130 writel(addr, PCI_IO_ADDR);
131 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
132 return (readl(PCI_IO_DATA_PORT) & 0xffff);
133}
134
135static inline u32 au_pci_io_readl(u32 addr)
136{
137 writel(addr, PCI_IO_ADDR);
138 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff), PCI_BRIDGE_CONFIG);
139 return readl(PCI_IO_DATA_PORT);
140}
141
142static inline void au_pci_io_writeb(u8 val, u32 addr)
143{
144 writel(addr, PCI_IO_ADDR);
145 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
146 writel(val, PCI_IO_DATA_PORT);
147}
148
149static inline void au_pci_io_writew(u16 val, u32 addr)
150{
151 writel(addr, PCI_IO_ADDR);
152 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
153 writel(val, PCI_IO_DATA_PORT);
154}
155
156static inline void au_pci_io_writel(u32 val, u32 addr)
157{
158 writel(addr, PCI_IO_ADDR);
159 writel(readl(PCI_BRIDGE_CONFIG) & 0xffffcfff, PCI_BRIDGE_CONFIG);
160 writel(val, PCI_IO_DATA_PORT);
161}
162
163static inline void set_sdram_extbyte(void)
164{
165 writel(readl(PCI_BRIDGE_CONFIG) & 0xffffff00, PCI_BRIDGE_CONFIG);
166}
167
168static inline void set_slot_extbyte(void)
169{
170 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG);
171}
172#endif /* __ASM_PB1000_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h
new file mode 100644
index 000000000000..4c5a1cd01841
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/pb1100.h
@@ -0,0 +1,85 @@
1/*
2 * Alchemy Semi PB1100 Referrence Board
3 *
4 * Copyright 2001 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc.
6 * ppopov@mvista.com or source@mvista.com
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_PB1100_H
28#define __ASM_PB1100_H
29
30#define PB1100_IDENT 0xAE000000
31#define BOARD_STATUS_REG 0xAE000004
32 #define PB1100_ROM_SEL (1<<15)
33 #define PB1100_ROM_SIZ (1<<14)
34 #define PB1100_SWAP_BOOT (1<<13)
35 #define PB1100_FLASH_WP (1<<12)
36 #define PB1100_ROM_H_STS (1<<11)
37 #define PB1100_ROM_L_STS (1<<10)
38 #define PB1100_FLASH_H_STS (1<<9)
39 #define PB1100_FLASH_L_STS (1<<8)
40 #define PB1100_SRAM_SIZ (1<<7)
41 #define PB1100_TSC_BUSY (1<<6)
42 #define PB1100_PCMCIA_VS_MASK (3<<4)
43 #define PB1100_RS232_CD (1<<3)
44 #define PB1100_RS232_CTS (1<<2)
45 #define PB1100_RS232_DSR (1<<1)
46 #define PB1100_RS232_RI (1<<0)
47
48#define PB1100_IRDA_RS232 0xAE00000C
49 #define PB1100_IRDA_FULL (0<<14) /* full power */
50 #define PB1100_IRDA_SHUTDOWN (1<<14)
51 #define PB1100_IRDA_TT (2<<14) /* 2/3 power */
52 #define PB1100_IRDA_OT (3<<14) /* 1/3 power */
53 #define PB1100_IRDA_FIR (1<<13)
54
55#define PCMCIA_BOARD_REG 0xAE000010
56 #define PB1100_SD_WP1_RO (1<<15) /* read only */
57 #define PB1100_SD_WP0_RO (1<<14) /* read only */
58 #define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */
59 #define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */
60 #define PB1100_SEL_SD_CONN1 (1<<9)
61 #define PB1100_SEL_SD_CONN0 (1<<8)
62 #define PC_DEASSERT_RST (1<<7)
63 #define PC_DRV_EN (1<<4)
64
65#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
66
67#define PB1100_RST_VDDI 0xAE00001C
68 #define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */
69 #define PB1100_VDDI_MASK (0x1F)
70
71#define PB1100_LEDS 0xAE000018
72
73/* 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
74 * 7:0 is the LED Display's decimal points.
75 */
76#define PB1100_HEX_LED 0xAE000018
77
78/* PCMCIA PB1100 specific defines */
79#define PCMCIA_MAX_SOCK 0
80#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
81
82/* VPP/VCC */
83#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0))
84
85#endif /* __ASM_PB1100_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h
new file mode 100644
index 000000000000..d6c779747b3c
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/pb1500.h
@@ -0,0 +1,51 @@
1/*
2 * Alchemy Semi PB1500 Referrence Board
3 *
4 * Copyright 2001 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc.
6 * ppopov@mvista.com or source@mvista.com
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_PB1500_H
28#define __ASM_PB1500_H
29
30
31#define IDENT_BOARD_REG 0xAE000000
32#define BOARD_STATUS_REG 0xAE000004
33#define PCI_BOARD_REG 0xAE000010
34#define PCMCIA_BOARD_REG 0xAE000010
35 #define PC_DEASSERT_RST 0x80
36 #define PC_DRV_EN 0x10
37#define PB1500_G_CONTROL 0xAE000014
38#define PB1500_RST_VDDI 0xAE00001C
39#define PB1500_LEDS 0xAE000018
40
41#define PB1500_HEX_LED 0xAF000004
42#define PB1500_HEX_LED_BLANK 0xAF000008
43
44/* PCMCIA PB1500 specific defines */
45#define PCMCIA_MAX_SOCK 0
46#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
47
48/* VPP/VCC */
49#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0))
50
51#endif /* __ASM_PB1500_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1550.h b/include/asm-mips/mach-pb1x00/pb1550.h
new file mode 100644
index 000000000000..431d6088ea96
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/pb1550.h
@@ -0,0 +1,169 @@
1/*
2 * AMD Alchemy Semi PB1550 Referrence Board
3 * Board Registers defines.
4 *
5 * Copyright 2004 Embedded Edge LLC.
6 * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_PB1550_H
28#define __ASM_PB1550_H
29
30#include <linux/config.h>
31#include <linux/types.h>
32
33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
37
38#define SPI_PSC_BASE PSC0_BASE_ADDR
39#define AC97_PSC_BASE PSC1_BASE_ADDR
40#define SMBUS_PSC_BASE PSC2_BASE_ADDR
41#define I2S_PSC_BASE PSC3_BASE_ADDR
42
43#define BCSR_PHYS_ADDR 0xAF000000
44
45typedef volatile struct
46{
47 /*00*/ u16 whoami;
48 u16 reserved0;
49 /*04*/ u16 status;
50 u16 reserved1;
51 /*08*/ u16 switches;
52 u16 reserved2;
53 /*0C*/ u16 resets;
54 u16 reserved3;
55 /*10*/ u16 pcmcia;
56 u16 reserved4;
57 /*14*/ u16 pci;
58 u16 reserved5;
59 /*18*/ u16 leds;
60 u16 reserved6;
61 /*1C*/ u16 system;
62 u16 reserved7;
63
64} BCSR;
65
66static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
67
68/*
69 * Register bit definitions for the BCSRs
70 */
71#define BCSR_WHOAMI_DCID 0x000F
72#define BCSR_WHOAMI_CPLD 0x00F0
73#define BCSR_WHOAMI_BOARD 0x0F00
74
75#define BCSR_STATUS_PCMCIA0VS 0x0003
76#define BCSR_STATUS_PCMCIA1VS 0x000C
77#define BCSR_STATUS_PCMCIA0FI 0x0010
78#define BCSR_STATUS_PCMCIA1FI 0x0020
79#define BCSR_STATUS_SWAPBOOT 0x0040
80#define BCSR_STATUS_SRAMWIDTH 0x0080
81#define BCSR_STATUS_FLASHBUSY 0x0100
82#define BCSR_STATUS_ROMBUSY 0x0200
83#define BCSR_STATUS_USBOTGID 0x0800
84#define BCSR_STATUS_U0RXD 0x1000
85#define BCSR_STATUS_U1RXD 0x2000
86#define BCSR_STATUS_U3RXD 0x8000
87
88#define BCSR_SWITCHES_OCTAL 0x00FF
89#define BCSR_SWITCHES_DIP_1 0x0080
90#define BCSR_SWITCHES_DIP_2 0x0040
91#define BCSR_SWITCHES_DIP_3 0x0020
92#define BCSR_SWITCHES_DIP_4 0x0010
93#define BCSR_SWITCHES_DIP_5 0x0008
94#define BCSR_SWITCHES_DIP_6 0x0004
95#define BCSR_SWITCHES_DIP_7 0x0002
96#define BCSR_SWITCHES_DIP_8 0x0001
97#define BCSR_SWITCHES_ROTARY 0x0F00
98
99#define BCSR_RESETS_PHY0 0x0001
100#define BCSR_RESETS_PHY1 0x0002
101#define BCSR_RESETS_DC 0x0004
102#define BCSR_RESETS_WSC 0x2000
103#define BCSR_RESETS_SPISEL 0x4000
104#define BCSR_RESETS_DMAREQ 0x8000
105
106#define BCSR_PCMCIA_PC0VPP 0x0003
107#define BCSR_PCMCIA_PC0VCC 0x000C
108#define BCSR_PCMCIA_PC0DRVEN 0x0010
109#define BCSR_PCMCIA_PC0RST 0x0080
110#define BCSR_PCMCIA_PC1VPP 0x0300
111#define BCSR_PCMCIA_PC1VCC 0x0C00
112#define BCSR_PCMCIA_PC1DRVEN 0x1000
113#define BCSR_PCMCIA_PC1RST 0x8000
114
115#define BCSR_PCI_M66EN 0x0001
116#define BCSR_PCI_M33 0x0100
117#define BCSR_PCI_EXTERNARB 0x0200
118#define BCSR_PCI_GPIO200RST 0x0400
119#define BCSR_PCI_CLKOUT 0x0800
120#define BCSR_PCI_CFGHOST 0x1000
121
122#define BCSR_LEDS_DECIMALS 0x00FF
123#define BCSR_LEDS_LED0 0x0100
124#define BCSR_LEDS_LED1 0x0200
125#define BCSR_LEDS_LED2 0x0400
126#define BCSR_LEDS_LED3 0x0800
127
128#define BCSR_SYSTEM_VDDI 0x001F
129#define BCSR_SYSTEM_POWEROFF 0x4000
130#define BCSR_SYSTEM_RESET 0x8000
131
132#define PCMCIA_MAX_SOCK 1
133#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
134
135/* VPP/VCC */
136#define SET_VCC_VPP(VCC, VPP, SLOT)\
137 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
138
139#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
140#define PB1550_BOTH_BANKS
141#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
142#define PB1550_BOOT_ONLY
143#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
144#define PB1550_USER_ONLY
145#endif
146
147/* Timing values as described in databook, * ns value stripped of
148 * lower 2 bits.
149 * These defines are here rather than an SOC1550 generic file because
150 * the parts chosen on another board may be different and may require
151 * different timings.
152 */
153#define NAND_T_H (18 >> 2)
154#define NAND_T_PUL (30 >> 2)
155#define NAND_T_SU (30 >> 2)
156#define NAND_T_WH (30 >> 2)
157
158/* Bitfield shift amounts */
159#define NAND_T_H_SHIFT 0
160#define NAND_T_PUL_SHIFT 4
161#define NAND_T_SU_SHIFT 8
162#define NAND_T_WH_SHIFT 12
163
164#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
165 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
166 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
167 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
168
169#endif /* __ASM_PB1550_H */
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