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-rw-r--r--include/asm-mips/mach-ip32/cpu-feature-overrides.h50
-rw-r--r--include/asm-mips/mach-ip32/dma-coherence.h72
-rw-r--r--include/asm-mips/mach-ip32/kmalloc.h11
-rw-r--r--include/asm-mips/mach-ip32/mangle-port.h26
-rw-r--r--include/asm-mips/mach-ip32/mc146818rtc.h36
-rw-r--r--include/asm-mips/mach-ip32/war.h25
6 files changed, 0 insertions, 220 deletions
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
deleted file mode 100644
index 6782fccebe8d..000000000000
--- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 Ilya A. Volynets-Evenbakh
7 * Copyright (C) 2005, 07 Ralf Baechle (ralf@linux-mips.org)
8 */
9#ifndef __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
11
12
13/*
14 * R5000 has an interesting "restriction": ll(d)/sc(d)
15 * instructions to XKPHYS region simply do uncached bus
16 * requests. This breaks all the atomic bitops functions.
17 * so, for 64bit IP32 kernel we just don't use ll/sc.
18 * This does not affect luserland.
19 */
20#if (defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_NEVADA)) && defined(CONFIG_64BIT)
21#define cpu_has_llsc 0
22#else
23#define cpu_has_llsc 1
24#endif
25
26/* Settings which are common for all ip32 CPUs */
27#define cpu_has_tlb 1
28#define cpu_has_4kex 1
29#define cpu_has_fpu 1
30#define cpu_has_32fpr 1
31#define cpu_has_counter 1
32#define cpu_has_mips16 0
33#define cpu_has_vce 0
34#define cpu_has_cache_cdex_s 0
35#define cpu_has_mcheck 0
36#define cpu_has_ejtag 0
37#define cpu_has_vtag_icache 0
38#define cpu_has_ic_fills_f_dc 0
39#define cpu_has_dsp 0
40#define cpu_has_4k_cache 1
41#define cpu_has_mipsmt 0
42#define cpu_has_userlocal 0
43
44
45#define cpu_has_mips32r1 0
46#define cpu_has_mips32r2 0
47#define cpu_has_mips64r1 0
48#define cpu_has_mips64r2 0
49
50#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip32/dma-coherence.h b/include/asm-mips/mach-ip32/dma-coherence.h
deleted file mode 100644
index a5511ebb2d53..000000000000
--- a/include/asm-mips/mach-ip32/dma-coherence.h
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
7 *
8 */
9#ifndef __ASM_MACH_IP32_DMA_COHERENCE_H
10#define __ASM_MACH_IP32_DMA_COHERENCE_H
11
12#include <asm/ip32/crime.h>
13
14struct device;
15
16/*
17 * Few notes.
18 * 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M
19 * 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for
20 * native-endian)
21 * 3. All other devices see memory as one big chunk at 0x40000000
22 * 4. Non-PCI devices will pass NULL as struct device*
23 *
24 * Thus we translate differently, depending on device.
25 */
26
27#define RAM_OFFSET_MASK 0x3fffffffUL
28
29static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
30 size_t size)
31{
32 dma_addr_t pa = virt_to_phys(addr) & RAM_OFFSET_MASK;
33
34 if (dev == NULL)
35 pa += CRIME_HI_MEM_BASE;
36
37 return pa;
38}
39
40static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
41{
42 dma_addr_t pa;
43
44 pa = page_to_phys(page) & RAM_OFFSET_MASK;
45
46 if (dev == NULL)
47 pa += CRIME_HI_MEM_BASE;
48
49 return pa;
50}
51
52/* This is almost certainly wrong but it's what dma-ip32.c used to use */
53static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
54{
55 unsigned long addr = dma_addr & RAM_OFFSET_MASK;
56
57 if (dma_addr >= 256*1024*1024)
58 addr += CRIME_HI_MEM_BASE;
59
60 return addr;
61}
62
63static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
64{
65}
66
67static inline int plat_device_is_coherent(struct device *dev)
68{
69 return 0; /* IP32 is non-cohernet */
70}
71
72#endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */
diff --git a/include/asm-mips/mach-ip32/kmalloc.h b/include/asm-mips/mach-ip32/kmalloc.h
deleted file mode 100644
index b1e0be60f720..000000000000
--- a/include/asm-mips/mach-ip32/kmalloc.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef __ASM_MACH_IP32_KMALLOC_H
2#define __ASM_MACH_IP32_KMALLOC_H
3
4
5#if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000)
6#define ARCH_KMALLOC_MINALIGN 32
7#else
8#define ARCH_KMALLOC_MINALIGN 128
9#endif
10
11#endif /* __ASM_MACH_IP32_KMALLOC_H */
diff --git a/include/asm-mips/mach-ip32/mangle-port.h b/include/asm-mips/mach-ip32/mangle-port.h
deleted file mode 100644
index f1d0f1756a9f..000000000000
--- a/include/asm-mips/mach-ip32/mangle-port.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Ladislav Michl
7 * Copyright (C) 2004 Ralf Baechle
8 */
9#ifndef __ASM_MACH_IP32_MANGLE_PORT_H
10#define __ASM_MACH_IP32_MANGLE_PORT_H
11
12#define __swizzle_addr_b(port) ((port) ^ 3)
13#define __swizzle_addr_w(port) ((port) ^ 2)
14#define __swizzle_addr_l(port) (port)
15#define __swizzle_addr_q(port) (port)
16
17# define ioswabb(a, x) (x)
18# define __mem_ioswabb(a, x) (x)
19# define ioswabw(a, x) (x)
20# define __mem_ioswabw(a, x) cpu_to_le16(x)
21# define ioswabl(a, x) (x)
22# define __mem_ioswabl(a, x) cpu_to_le32(x)
23# define ioswabq(a, x) (x)
24# define __mem_ioswabq(a, x) cpu_to_le32(x)
25
26#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-ip32/mc146818rtc.h b/include/asm-mips/mach-ip32/mc146818rtc.h
deleted file mode 100644
index c28ba8d84076..000000000000
--- a/include/asm-mips/mach-ip32/mc146818rtc.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998, 2001, 03 by Ralf Baechle
7 * Copyright (C) 2000 Harald Koerfgen
8 *
9 * RTC routines for IP32 style attached Dallas chip.
10 */
11#ifndef __ASM_MACH_IP32_MC146818RTC_H
12#define __ASM_MACH_IP32_MC146818RTC_H
13
14#include <asm/ip32/mace.h>
15
16#define RTC_PORT(x) (0x70 + (x))
17
18static unsigned char CMOS_READ(unsigned long addr)
19{
20 return mace->isa.rtc[addr << 8];
21}
22
23static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
24{
25 mace->isa.rtc[addr << 8] = data;
26}
27
28/*
29 * FIXME: Do it right. For now just assume that noone lives in 20th century
30 * and no O2 user in 22th century ;-)
31 */
32#define mc146818_decode_year(year) ((year) + 2000)
33
34#define RTC_ALWAYS_BCD 0
35
36#endif /* __ASM_MACH_IP32_MC146818RTC_H */
diff --git a/include/asm-mips/mach-ip32/war.h b/include/asm-mips/mach-ip32/war.h
deleted file mode 100644
index d194056dcd7a..000000000000
--- a/include/asm-mips/mach-ip32/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_IP32_WAR_H
9#define __ASM_MIPS_MACH_IP32_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 10:01:44 -0500