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-rw-r--r--include/asm-mips/mach-cobalt/cobalt.h22
-rw-r--r--include/asm-mips/mach-cobalt/cpu-feature-overrides.h56
-rw-r--r--include/asm-mips/mach-cobalt/irq.h57
-rw-r--r--include/asm-mips/mach-cobalt/mach-gt64120.h27
-rw-r--r--include/asm-mips/mach-cobalt/war.h25
5 files changed, 0 insertions, 187 deletions
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
deleted file mode 100644
index 5b9fce73f11d..000000000000
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * The Cobalt board ID information.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1997 Cobalt Microserver
9 * Copyright (C) 1997, 2003 Ralf Baechle
10 * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv)
11 */
12#ifndef __ASM_COBALT_H
13#define __ASM_COBALT_H
14
15extern int cobalt_board_id;
16
17#define COBALT_BRD_ID_QUBE1 0x3
18#define COBALT_BRD_ID_RAQ1 0x4
19#define COBALT_BRD_ID_QUBE2 0x5
20#define COBALT_BRD_ID_RAQ2 0x6
21
22#endif /* __ASM_COBALT_H */
diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
deleted file mode 100644
index b3314cf53194..000000000000
--- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
9#define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
10
11
12#define cpu_has_tlb 1
13#define cpu_has_4kex 1
14#define cpu_has_3k_cache 0
15#define cpu_has_4k_cache 1
16#define cpu_has_tx39_cache 0
17#define cpu_has_fpu 1
18#define cpu_has_32fpr 1
19#define cpu_has_counter 1
20#define cpu_has_watch 0
21#define cpu_has_divec 1
22#define cpu_has_vce 0
23#define cpu_has_cache_cdex_p 0
24#define cpu_has_cache_cdex_s 0
25#define cpu_has_prefetch 0
26#define cpu_has_mcheck 0
27#define cpu_has_ejtag 0
28
29#define cpu_has_inclusive_pcaches 0
30#define cpu_dcache_line_size() 32
31#define cpu_icache_line_size() 32
32#define cpu_scache_line_size() 0
33
34#ifdef CONFIG_64BIT
35#define cpu_has_llsc 0
36#else
37#define cpu_has_llsc 1
38#endif
39
40#define cpu_has_mips16 0
41#define cpu_has_mdmx 0
42#define cpu_has_mips3d 0
43#define cpu_has_smartmips 0
44#define cpu_has_vtag_icache 0
45#define cpu_has_ic_fills_f_dc 0
46#define cpu_icache_snoops_remote_store 0
47#define cpu_has_dsp 0
48#define cpu_has_mipsmt 0
49#define cpu_has_userlocal 0
50
51#define cpu_has_mips32r1 0
52#define cpu_has_mips32r2 0
53#define cpu_has_mips64r1 0
54#define cpu_has_mips64r2 0
55
56#endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h
deleted file mode 100644
index 57c8c9ac5851..000000000000
--- a/include/asm-mips/mach-cobalt/irq.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * Cobalt IRQ definitions.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1997 Cobalt Microserver
9 * Copyright (C) 1997, 2003 Ralf Baechle
10 * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv)
11 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
12 */
13#ifndef _ASM_COBALT_IRQ_H
14#define _ASM_COBALT_IRQ_H
15
16/*
17 * i8259 interrupts used on Cobalt:
18 *
19 * 8 - RTC
20 * 9 - PCI slot
21 * 14 - IDE0
22 * 15 - IDE1(no connector on board)
23 */
24#define I8259A_IRQ_BASE 0
25
26#define PCISLOT_IRQ (I8259A_IRQ_BASE + 9)
27
28/*
29 * CPU interrupts used on Cobalt:
30 *
31 * 0 - Software interrupt 0 (unused)
32 * 1 - Software interrupt 0 (unused)
33 * 2 - cascade GT64111
34 * 3 - ethernet or SCSI host controller
35 * 4 - ethernet
36 * 5 - 16550 UART
37 * 6 - cascade i8259
38 * 7 - CP0 counter
39 */
40#define MIPS_CPU_IRQ_BASE 16
41
42#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
43#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3)
44#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3)
45#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4)
46#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4)
47#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5)
48#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
49#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
50
51#define GT641XX_IRQ_BASE 24
52
53#include <asm/irq_gt641xx.h>
54
55#define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1)
56
57#endif /* _ASM_COBALT_IRQ_H */
diff --git a/include/asm-mips/mach-cobalt/mach-gt64120.h b/include/asm-mips/mach-cobalt/mach-gt64120.h
deleted file mode 100644
index ae9c5523c7ef..000000000000
--- a/include/asm-mips/mach-cobalt/mach-gt64120.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Copyright (C) 2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#ifndef _COBALT_MACH_GT64120_H
19#define _COBALT_MACH_GT64120_H
20
21/*
22 * Cobalt uses GT64111. GT64111 is almost the same as GT64120.
23 */
24
25#define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE)
26
27#endif /* _COBALT_MACH_GT64120_H */
diff --git a/include/asm-mips/mach-cobalt/war.h b/include/asm-mips/mach-cobalt/war.h
deleted file mode 100644
index 97884fd18ac0..000000000000
--- a/include/asm-mips/mach-cobalt/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_COBALT_WAR_H
9#define __ASM_MIPS_MACH_COBALT_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_COBALT_WAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 22:15:54 -0500