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Diffstat (limited to 'include/asm-mips/mach-au1x00/au1xxx_psc.h')
-rw-r--r-- | include/asm-mips/mach-au1x00/au1xxx_psc.h | 522 |
1 files changed, 522 insertions, 0 deletions
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h new file mode 100644 index 000000000000..283519dfdec4 --- /dev/null +++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h | |||
@@ -0,0 +1,522 @@ | |||
1 | /* | ||
2 | * | ||
3 | * BRIEF MODULE DESCRIPTION | ||
4 | * Include file for Alchemy Semiconductor's Au1k CPU. | ||
5 | * | ||
6 | * Copyright 2004 Embedded Edge, LLC | ||
7 | * dan@embeddededge.com | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify it | ||
10 | * under the terms of the GNU General Public License as published by the | ||
11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
12 | * option) any later version. | ||
13 | * | ||
14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
15 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
20 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
21 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
24 | * | ||
25 | * You should have received a copy of the GNU General Public License along | ||
26 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
28 | */ | ||
29 | |||
30 | /* Specifics for the Au1xxx Programmable Serial Controllers, first | ||
31 | * seen in the AU1550 part. | ||
32 | */ | ||
33 | #ifndef _AU1000_PSC_H_ | ||
34 | #define _AU1000_PSC_H_ | ||
35 | |||
36 | /* The PSC base addresses. */ | ||
37 | #ifdef CONFIG_SOC_AU1550 | ||
38 | #define PSC0_BASE_ADDR 0xb1a00000 | ||
39 | #define PSC1_BASE_ADDR 0xb1b00000 | ||
40 | #define PSC2_BASE_ADDR 0xb0a00000 | ||
41 | #define PSC3_BASE_ADDR 0xb0d00000 | ||
42 | #endif | ||
43 | |||
44 | /* The PSC select and control registers are common to | ||
45 | * all protocols. | ||
46 | */ | ||
47 | #define PSC_SEL_OFFSET 0x00000000 | ||
48 | #define PSC_CTRL_OFFSET 0x00000004 | ||
49 | |||
50 | #define PSC_SEL_CLK_MASK (3 << 4) | ||
51 | #define PSC_SEL_CLK_INTCLK (0 << 4) | ||
52 | #define PSC_SEL_CLK_EXTCLK (1 << 4) | ||
53 | #define PSC_SEL_CLK_SERCLK (2 << 4) | ||
54 | |||
55 | #define PSC_SEL_PS_MASK 0x00000007 | ||
56 | #define PSC_SEL_PS_DISABLED (0) | ||
57 | #define PSC_SEL_PS_SPIMODE (2) | ||
58 | #define PSC_SEL_PS_I2SMODE (3) | ||
59 | #define PSC_SEL_PS_AC97MODE (4) | ||
60 | #define PSC_SEL_PS_SMBUSMODE (5) | ||
61 | |||
62 | #define PSC_CTRL_DISABLE (0) | ||
63 | #define PSC_CTRL_SUSPEND (2) | ||
64 | #define PSC_CTRL_ENABLE (3) | ||
65 | |||
66 | /* AC97 Registers. | ||
67 | */ | ||
68 | #define PSC_AC97CFG_OFFSET 0x00000008 | ||
69 | #define PSC_AC97MSK_OFFSET 0x0000000c | ||
70 | #define PSC_AC97PCR_OFFSET 0x00000010 | ||
71 | #define PSC_AC97STAT_OFFSET 0x00000014 | ||
72 | #define PSC_AC97EVNT_OFFSET 0x00000018 | ||
73 | #define PSC_AC97TXRX_OFFSET 0x0000001c | ||
74 | #define PSC_AC97CDC_OFFSET 0x00000020 | ||
75 | #define PSC_AC97RST_OFFSET 0x00000024 | ||
76 | #define PSC_AC97GPO_OFFSET 0x00000028 | ||
77 | #define PSC_AC97GPI_OFFSET 0x0000002c | ||
78 | |||
79 | #define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET) | ||
80 | #define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET) | ||
81 | #define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET) | ||
82 | #define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET) | ||
83 | #define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET) | ||
84 | #define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET) | ||
85 | #define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET) | ||
86 | #define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET) | ||
87 | #define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET) | ||
88 | #define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET) | ||
89 | #define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET) | ||
90 | #define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET) | ||
91 | |||
92 | /* AC97 Config Register. | ||
93 | */ | ||
94 | #define PSC_AC97CFG_RT_MASK (3 << 30) | ||
95 | #define PSC_AC97CFG_RT_FIFO1 (0 << 30) | ||
96 | #define PSC_AC97CFG_RT_FIFO2 (1 << 30) | ||
97 | #define PSC_AC97CFG_RT_FIFO4 (2 << 30) | ||
98 | #define PSC_AC97CFG_RT_FIFO8 (3 << 30) | ||
99 | |||
100 | #define PSC_AC97CFG_TT_MASK (3 << 28) | ||
101 | #define PSC_AC97CFG_TT_FIFO1 (0 << 28) | ||
102 | #define PSC_AC97CFG_TT_FIFO2 (1 << 28) | ||
103 | #define PSC_AC97CFG_TT_FIFO4 (2 << 28) | ||
104 | #define PSC_AC97CFG_TT_FIFO8 (3 << 28) | ||
105 | |||
106 | #define PSC_AC97CFG_DD_DISABLE (1 << 27) | ||
107 | #define PSC_AC97CFG_DE_ENABLE (1 << 26) | ||
108 | #define PSC_AC97CFG_SE_ENABLE (1 << 25) | ||
109 | |||
110 | #define PSC_AC97CFG_LEN_MASK (0xf << 21) | ||
111 | #define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11) | ||
112 | #define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) | ||
113 | #define PSC_AC97CFG_GE_ENABLE (1) | ||
114 | |||
115 | /* Enable slots 3-12. | ||
116 | */ | ||
117 | #define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11)) | ||
118 | #define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1)) | ||
119 | |||
120 | /* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately. | ||
121 | * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the | ||
122 | * arithmetic in the macro. | ||
123 | */ | ||
124 | #define PSC_AC97CFG_SET_LEN(x) (((((x)-2)/2) & 0xf) << 21) | ||
125 | #define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2) | ||
126 | |||
127 | /* AC97 Mask Register. | ||
128 | */ | ||
129 | #define PSC_AC97MSK_GR (1 << 25) | ||
130 | #define PSC_AC97MSK_CD (1 << 24) | ||
131 | #define PSC_AC97MSK_RR (1 << 13) | ||
132 | #define PSC_AC97MSK_RO (1 << 12) | ||
133 | #define PSC_AC97MSK_RU (1 << 11) | ||
134 | #define PSC_AC97MSK_TR (1 << 10) | ||
135 | #define PSC_AC97MSK_TO (1 << 9) | ||
136 | #define PSC_AC97MSK_TU (1 << 8) | ||
137 | #define PSC_AC97MSK_RD (1 << 5) | ||
138 | #define PSC_AC97MSK_TD (1 << 4) | ||
139 | #define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \ | ||
140 | PSC_AC97MSK_RR | PSC_AC97MSK_RO | \ | ||
141 | PSC_AC97MSK_RU | PSC_AC97MSK_TR | \ | ||
142 | PSC_AC97MSK_TO | PSC_AC97MSK_TU | \ | ||
143 | PSC_AC97MSK_RD | PSC_AC97MSK_TD) | ||
144 | |||
145 | /* AC97 Protocol Control Register. | ||
146 | */ | ||
147 | #define PSC_AC97PCR_RC (1 << 6) | ||
148 | #define PSC_AC97PCR_RP (1 << 5) | ||
149 | #define PSC_AC97PCR_RS (1 << 4) | ||
150 | #define PSC_AC97PCR_TC (1 << 2) | ||
151 | #define PSC_AC97PCR_TP (1 << 1) | ||
152 | #define PSC_AC97PCR_TS (1 << 0) | ||
153 | |||
154 | /* AC97 Status register (read only). | ||
155 | */ | ||
156 | #define PSC_AC97STAT_CB (1 << 26) | ||
157 | #define PSC_AC97STAT_CP (1 << 25) | ||
158 | #define PSC_AC97STAT_CR (1 << 24) | ||
159 | #define PSC_AC97STAT_RF (1 << 13) | ||
160 | #define PSC_AC97STAT_RE (1 << 12) | ||
161 | #define PSC_AC97STAT_RR (1 << 11) | ||
162 | #define PSC_AC97STAT_TF (1 << 10) | ||
163 | #define PSC_AC97STAT_TE (1 << 9) | ||
164 | #define PSC_AC97STAT_TR (1 << 8) | ||
165 | #define PSC_AC97STAT_RB (1 << 5) | ||
166 | #define PSC_AC97STAT_TB (1 << 4) | ||
167 | #define PSC_AC97STAT_DI (1 << 2) | ||
168 | #define PSC_AC97STAT_DR (1 << 1) | ||
169 | #define PSC_AC97STAT_SR (1 << 0) | ||
170 | |||
171 | /* AC97 Event Register. | ||
172 | */ | ||
173 | #define PSC_AC97EVNT_GR (1 << 25) | ||
174 | #define PSC_AC97EVNT_CD (1 << 24) | ||
175 | #define PSC_AC97EVNT_RR (1 << 13) | ||
176 | #define PSC_AC97EVNT_RO (1 << 12) | ||
177 | #define PSC_AC97EVNT_RU (1 << 11) | ||
178 | #define PSC_AC97EVNT_TR (1 << 10) | ||
179 | #define PSC_AC97EVNT_TO (1 << 9) | ||
180 | #define PSC_AC97EVNT_TU (1 << 8) | ||
181 | #define PSC_AC97EVNT_RD (1 << 5) | ||
182 | #define PSC_AC97EVNT_TD (1 << 4) | ||
183 | |||
184 | /* CODEC Command Register. | ||
185 | */ | ||
186 | #define PSC_AC97CDC_RD (1 << 25) | ||
187 | #define PSC_AC97CDC_ID_MASK (3 << 23) | ||
188 | #define PSC_AC97CDC_INDX_MASK (0x7f << 16) | ||
189 | #define PSC_AC97CDC_ID(x) (((x) & 0x3) << 23) | ||
190 | #define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16) | ||
191 | |||
192 | /* AC97 Reset Control Register. | ||
193 | */ | ||
194 | #define PSC_AC97RST_RST (1 << 1) | ||
195 | #define PSC_AC97RST_SNC (1 << 0) | ||
196 | |||
197 | |||
198 | /* PSC in I2S Mode. | ||
199 | */ | ||
200 | typedef struct psc_i2s { | ||
201 | u32 psc_sel; | ||
202 | u32 psc_ctrl; | ||
203 | u32 psc_i2scfg; | ||
204 | u32 psc_i2smsk; | ||
205 | u32 psc_i2spcr; | ||
206 | u32 psc_i2sstat; | ||
207 | u32 psc_i2sevent; | ||
208 | u32 psc_i2stxrx; | ||
209 | u32 psc_i2sudf; | ||
210 | } psc_i2s_t; | ||
211 | |||
212 | /* I2S Config Register. | ||
213 | */ | ||
214 | #define PSC_I2SCFG_RT_MASK (3 << 30) | ||
215 | #define PSC_I2SCFG_RT_FIFO1 (0 << 30) | ||
216 | #define PSC_I2SCFG_RT_FIFO2 (1 << 30) | ||
217 | #define PSC_I2SCFG_RT_FIFO4 (2 << 30) | ||
218 | #define PSC_I2SCFG_RT_FIFO8 (3 << 30) | ||
219 | |||
220 | #define PSC_I2SCFG_TT_MASK (3 << 28) | ||
221 | #define PSC_I2SCFG_TT_FIFO1 (0 << 28) | ||
222 | #define PSC_I2SCFG_TT_FIFO2 (1 << 28) | ||
223 | #define PSC_I2SCFG_TT_FIFO4 (2 << 28) | ||
224 | #define PSC_I2SCFG_TT_FIFO8 (3 << 28) | ||
225 | |||
226 | #define PSC_I2SCFG_DD_DISABLE (1 << 27) | ||
227 | #define PSC_I2SCFG_DE_ENABLE (1 << 26) | ||
228 | #define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16) | ||
229 | #define PSC_I2SCFG_WI (1 << 15) | ||
230 | |||
231 | #define PSC_I2SCFG_DIV_MASK (3 << 13) | ||
232 | #define PSC_I2SCFG_DIV2 (0 << 13) | ||
233 | #define PSC_I2SCFG_DIV4 (1 << 13) | ||
234 | #define PSC_I2SCFG_DIV8 (2 << 13) | ||
235 | #define PSC_I2SCFG_DIV16 (3 << 13) | ||
236 | |||
237 | #define PSC_I2SCFG_BI (1 << 12) | ||
238 | #define PSC_I2SCFG_BUF (1 << 11) | ||
239 | #define PSC_I2SCFG_MLJ (1 << 10) | ||
240 | #define PSC_I2SCFG_XM (1 << 9) | ||
241 | |||
242 | /* The word length equation is simply LEN+1. | ||
243 | */ | ||
244 | #define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4) | ||
245 | #define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1) | ||
246 | |||
247 | #define PSC_I2SCFG_LB (1 << 2) | ||
248 | #define PSC_I2SCFG_MLF (1 << 1) | ||
249 | #define PSC_I2SCFG_MS (1 << 0) | ||
250 | |||
251 | /* I2S Mask Register. | ||
252 | */ | ||
253 | #define PSC_I2SMSK_RR (1 << 13) | ||
254 | #define PSC_I2SMSK_RO (1 << 12) | ||
255 | #define PSC_I2SMSK_RU (1 << 11) | ||
256 | #define PSC_I2SMSK_TR (1 << 10) | ||
257 | #define PSC_I2SMSK_TO (1 << 9) | ||
258 | #define PSC_I2SMSK_TU (1 << 8) | ||
259 | #define PSC_I2SMSK_RD (1 << 5) | ||
260 | #define PSC_I2SMSK_TD (1 << 4) | ||
261 | #define PSC_I2SMSK_ALLMASK (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \ | ||
262 | PSC_I2SMSK_RU | PSC_I2SMSK_TR | \ | ||
263 | PSC_I2SMSK_TO | PSC_I2SMSK_TU | \ | ||
264 | PSC_I2SMSK_RD | PSC_I2SMSK_TD) | ||
265 | |||
266 | /* I2S Protocol Control Register. | ||
267 | */ | ||
268 | #define PSC_I2SPCR_RC (1 << 6) | ||
269 | #define PSC_I2SPCR_RP (1 << 5) | ||
270 | #define PSC_I2SPCR_RS (1 << 4) | ||
271 | #define PSC_I2SPCR_TC (1 << 2) | ||
272 | #define PSC_I2SPCR_TP (1 << 1) | ||
273 | #define PSC_I2SPCR_TS (1 << 0) | ||
274 | |||
275 | /* I2S Status register (read only). | ||
276 | */ | ||
277 | #define PSC_I2SSTAT_RF (1 << 13) | ||
278 | #define PSC_I2SSTAT_RE (1 << 12) | ||
279 | #define PSC_I2SSTAT_RR (1 << 11) | ||
280 | #define PSC_I2SSTAT_TF (1 << 10) | ||
281 | #define PSC_I2SSTAT_TE (1 << 9) | ||
282 | #define PSC_I2SSTAT_TR (1 << 8) | ||
283 | #define PSC_I2SSTAT_RB (1 << 5) | ||
284 | #define PSC_I2SSTAT_TB (1 << 4) | ||
285 | #define PSC_I2SSTAT_DI (1 << 2) | ||
286 | #define PSC_I2SSTAT_DR (1 << 1) | ||
287 | #define PSC_I2SSTAT_SR (1 << 0) | ||
288 | |||
289 | /* I2S Event Register. | ||
290 | */ | ||
291 | #define PSC_I2SEVNT_RR (1 << 13) | ||
292 | #define PSC_I2SEVNT_RO (1 << 12) | ||
293 | #define PSC_I2SEVNT_RU (1 << 11) | ||
294 | #define PSC_I2SEVNT_TR (1 << 10) | ||
295 | #define PSC_I2SEVNT_TO (1 << 9) | ||
296 | #define PSC_I2SEVNT_TU (1 << 8) | ||
297 | #define PSC_I2SEVNT_RD (1 << 5) | ||
298 | #define PSC_I2SEVNT_TD (1 << 4) | ||
299 | |||
300 | /* PSC in SPI Mode. | ||
301 | */ | ||
302 | typedef struct psc_spi { | ||
303 | u32 psc_sel; | ||
304 | u32 psc_ctrl; | ||
305 | u32 psc_spicfg; | ||
306 | u32 psc_spimsk; | ||
307 | u32 psc_spipcr; | ||
308 | u32 psc_spistat; | ||
309 | u32 psc_spievent; | ||
310 | u32 psc_spitxrx; | ||
311 | } psc_spi_t; | ||
312 | |||
313 | /* SPI Config Register. | ||
314 | */ | ||
315 | #define PSC_SPICFG_RT_MASK (3 << 30) | ||
316 | #define PSC_SPICFG_RT_FIFO1 (0 << 30) | ||
317 | #define PSC_SPICFG_RT_FIFO2 (1 << 30) | ||
318 | #define PSC_SPICFG_RT_FIFO4 (2 << 30) | ||
319 | #define PSC_SPICFG_RT_FIFO8 (3 << 30) | ||
320 | |||
321 | #define PSC_SPICFG_TT_MASK (3 << 28) | ||
322 | #define PSC_SPICFG_TT_FIFO1 (0 << 28) | ||
323 | #define PSC_SPICFG_TT_FIFO2 (1 << 28) | ||
324 | #define PSC_SPICFG_TT_FIFO4 (2 << 28) | ||
325 | #define PSC_SPICFG_TT_FIFO8 (3 << 28) | ||
326 | |||
327 | #define PSC_SPICFG_DD_DISABLE (1 << 27) | ||
328 | #define PSC_SPICFG_DE_ENABLE (1 << 26) | ||
329 | #define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15)) | ||
330 | #define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15) | ||
331 | |||
332 | #define PSC_SPICFG_SET_DIV(x) (((x) & 0x03) << 13) | ||
333 | #define PSC_SPICFG_DIV2 0 | ||
334 | #define PSC_SPICFG_DIV4 1 | ||
335 | #define PSC_SPICFG_DIV8 2 | ||
336 | #define PSC_SPICFG_DIV16 3 | ||
337 | |||
338 | #define PSC_SPICFG_BI (1 << 12) | ||
339 | #define PSC_SPICFG_PSE (1 << 11) | ||
340 | #define PSC_SPICFG_CGE (1 << 10) | ||
341 | #define PSC_SPICFG_CDE (1 << 9) | ||
342 | |||
343 | #define PSC_SPICFG_CLR_LEN(x) ((x) & ~((0x1f) << 4)) | ||
344 | #define PSC_SPICFG_SET_LEN(x) (((x-1) & 0x1f) << 4) | ||
345 | |||
346 | #define PSC_SPICFG_LB (1 << 3) | ||
347 | #define PSC_SPICFG_MLF (1 << 1) | ||
348 | #define PSC_SPICFG_MO (1 << 0) | ||
349 | |||
350 | /* SPI Mask Register. | ||
351 | */ | ||
352 | #define PSC_SPIMSK_MM (1 << 16) | ||
353 | #define PSC_SPIMSK_RR (1 << 13) | ||
354 | #define PSC_SPIMSK_RO (1 << 12) | ||
355 | #define PSC_SPIMSK_RU (1 << 11) | ||
356 | #define PSC_SPIMSK_TR (1 << 10) | ||
357 | #define PSC_SPIMSK_TO (1 << 9) | ||
358 | #define PSC_SPIMSK_TU (1 << 8) | ||
359 | #define PSC_SPIMSK_SD (1 << 5) | ||
360 | #define PSC_SPIMSK_MD (1 << 4) | ||
361 | #define PSC_SPIMSK_ALLMASK (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \ | ||
362 | PSC_SPIMSK_RO | PSC_SPIMSK_TO | \ | ||
363 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | \ | ||
364 | PSC_SPIMSK_MD) | ||
365 | |||
366 | /* SPI Protocol Control Register. | ||
367 | */ | ||
368 | #define PSC_SPIPCR_RC (1 << 6) | ||
369 | #define PSC_SPIPCR_SP (1 << 5) | ||
370 | #define PSC_SPIPCR_SS (1 << 4) | ||
371 | #define PSC_SPIPCR_TC (1 << 2) | ||
372 | #define PSC_SPIPCR_MS (1 << 0) | ||
373 | |||
374 | /* SPI Status register (read only). | ||
375 | */ | ||
376 | #define PSC_SPISTAT_RF (1 << 13) | ||
377 | #define PSC_SPISTAT_RE (1 << 12) | ||
378 | #define PSC_SPISTAT_RR (1 << 11) | ||
379 | #define PSC_SPISTAT_TF (1 << 10) | ||
380 | #define PSC_SPISTAT_TE (1 << 9) | ||
381 | #define PSC_SPISTAT_TR (1 << 8) | ||
382 | #define PSC_SPISTAT_SB (1 << 5) | ||
383 | #define PSC_SPISTAT_MB (1 << 4) | ||
384 | #define PSC_SPISTAT_DI (1 << 2) | ||
385 | #define PSC_SPISTAT_DR (1 << 1) | ||
386 | #define PSC_SPISTAT_SR (1 << 0) | ||
387 | |||
388 | /* SPI Event Register. | ||
389 | */ | ||
390 | #define PSC_SPIEVNT_MM (1 << 16) | ||
391 | #define PSC_SPIEVNT_RR (1 << 13) | ||
392 | #define PSC_SPIEVNT_RO (1 << 12) | ||
393 | #define PSC_SPIEVNT_RU (1 << 11) | ||
394 | #define PSC_SPIEVNT_TR (1 << 10) | ||
395 | #define PSC_SPIEVNT_TO (1 << 9) | ||
396 | #define PSC_SPIEVNT_TU (1 << 8) | ||
397 | #define PSC_SPIEVNT_SD (1 << 5) | ||
398 | #define PSC_SPIEVNT_MD (1 << 4) | ||
399 | |||
400 | /* Transmit register control. | ||
401 | */ | ||
402 | #define PSC_SPITXRX_LC (1 << 29) | ||
403 | #define PSC_SPITXRX_SR (1 << 28) | ||
404 | |||
405 | /* PSC in SMBus (I2C) Mode. | ||
406 | */ | ||
407 | typedef struct psc_smb { | ||
408 | u32 psc_sel; | ||
409 | u32 psc_ctrl; | ||
410 | u32 psc_smbcfg; | ||
411 | u32 psc_smbmsk; | ||
412 | u32 psc_smbpcr; | ||
413 | u32 psc_smbstat; | ||
414 | u32 psc_smbevnt; | ||
415 | u32 psc_smbtxrx; | ||
416 | u32 psc_smbtmr; | ||
417 | } psc_smb_t; | ||
418 | |||
419 | /* SMBus Config Register. | ||
420 | */ | ||
421 | #define PSC_SMBCFG_RT_MASK (3 << 30) | ||
422 | #define PSC_SMBCFG_RT_FIFO1 (0 << 30) | ||
423 | #define PSC_SMBCFG_RT_FIFO2 (1 << 30) | ||
424 | #define PSC_SMBCFG_RT_FIFO4 (2 << 30) | ||
425 | #define PSC_SMBCFG_RT_FIFO8 (3 << 30) | ||
426 | |||
427 | #define PSC_SMBCFG_TT_MASK (3 << 28) | ||
428 | #define PSC_SMBCFG_TT_FIFO1 (0 << 28) | ||
429 | #define PSC_SMBCFG_TT_FIFO2 (1 << 28) | ||
430 | #define PSC_SMBCFG_TT_FIFO4 (2 << 28) | ||
431 | #define PSC_SMBCFG_TT_FIFO8 (3 << 28) | ||
432 | |||
433 | #define PSC_SMBCFG_DD_DISABLE (1 << 27) | ||
434 | #define PSC_SMBCFG_DE_ENABLE (1 << 26) | ||
435 | |||
436 | #define PSC_SMBCFG_SET_DIV(x) (((x) & 0x03) << 13) | ||
437 | #define PSC_SMBCFG_DIV2 0 | ||
438 | #define PSC_SMBCFG_DIV4 1 | ||
439 | #define PSC_SMBCFG_DIV8 2 | ||
440 | #define PSC_SMBCFG_DIV16 3 | ||
441 | |||
442 | #define PSC_SMBCFG_GCE (1 << 9) | ||
443 | #define PSC_SMBCFG_SFM (1 << 8) | ||
444 | |||
445 | #define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1) | ||
446 | |||
447 | /* SMBus Mask Register. | ||
448 | */ | ||
449 | #define PSC_SMBMSK_DN (1 << 30) | ||
450 | #define PSC_SMBMSK_AN (1 << 29) | ||
451 | #define PSC_SMBMSK_AL (1 << 28) | ||
452 | #define PSC_SMBMSK_RR (1 << 13) | ||
453 | #define PSC_SMBMSK_RO (1 << 12) | ||
454 | #define PSC_SMBMSK_RU (1 << 11) | ||
455 | #define PSC_SMBMSK_TR (1 << 10) | ||
456 | #define PSC_SMBMSK_TO (1 << 9) | ||
457 | #define PSC_SMBMSK_TU (1 << 8) | ||
458 | #define PSC_SMBMSK_SD (1 << 5) | ||
459 | #define PSC_SMBMSK_MD (1 << 4) | ||
460 | #define PSC_SMBMSK_ALLMASK (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \ | ||
461 | PSC_SMBMSK_AL | PSC_SMBMSK_RR | \ | ||
462 | PSC_SMBMSK_RO | PSC_SMBMSK_TO | \ | ||
463 | PSC_SMBMSK_TU | PSC_SMBMSK_SD | \ | ||
464 | PSC_SMBMSK_MD) | ||
465 | |||
466 | /* SMBus Protocol Control Register. | ||
467 | */ | ||
468 | #define PSC_SMBPCR_DC (1 << 2) | ||
469 | #define PSC_SMBPCR_MS (1 << 0) | ||
470 | |||
471 | /* SMBus Status register (read only). | ||
472 | */ | ||
473 | #define PSC_SMBSTAT_BB (1 << 28) | ||
474 | #define PSC_SMBSTAT_RF (1 << 13) | ||
475 | #define PSC_SMBSTAT_RE (1 << 12) | ||
476 | #define PSC_SMBSTAT_RR (1 << 11) | ||
477 | #define PSC_SMBSTAT_TF (1 << 10) | ||
478 | #define PSC_SMBSTAT_TE (1 << 9) | ||
479 | #define PSC_SMBSTAT_TR (1 << 8) | ||
480 | #define PSC_SMBSTAT_SB (1 << 5) | ||
481 | #define PSC_SMBSTAT_MB (1 << 4) | ||
482 | #define PSC_SMBSTAT_DI (1 << 2) | ||
483 | #define PSC_SMBSTAT_DR (1 << 1) | ||
484 | #define PSC_SMBSTAT_SR (1 << 0) | ||
485 | |||
486 | /* SMBus Event Register. | ||
487 | */ | ||
488 | #define PSC_SMBEVNT_DN (1 << 30) | ||
489 | #define PSC_SMBEVNT_AN (1 << 29) | ||
490 | #define PSC_SMBEVNT_AL (1 << 28) | ||
491 | #define PSC_SMBEVNT_RR (1 << 13) | ||
492 | #define PSC_SMBEVNT_RO (1 << 12) | ||
493 | #define PSC_SMBEVNT_RU (1 << 11) | ||
494 | #define PSC_SMBEVNT_TR (1 << 10) | ||
495 | #define PSC_SMBEVNT_TO (1 << 9) | ||
496 | #define PSC_SMBEVNT_TU (1 << 8) | ||
497 | #define PSC_SMBEVNT_SD (1 << 5) | ||
498 | #define PSC_SMBEVNT_MD (1 << 4) | ||
499 | #define PSC_SMBEVNT_ALLCLR (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \ | ||
500 | PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \ | ||
501 | PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \ | ||
502 | PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \ | ||
503 | PSC_SMBEVNT_MD) | ||
504 | |||
505 | /* Transmit register control. | ||
506 | */ | ||
507 | #define PSC_SMBTXRX_RSR (1 << 30) | ||
508 | #define PSC_SMBTXRX_STP (1 << 29) | ||
509 | #define PSC_SMBTXRX_DATAMASK (0xff) | ||
510 | |||
511 | /* SMBus protocol timers register. | ||
512 | */ | ||
513 | #define PSC_SMBTMR_SET_TH(x) (((x) & 0x3) << 30) | ||
514 | #define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25) | ||
515 | #define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20) | ||
516 | #define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15) | ||
517 | #define PSC_SMBTMR_SET_SU(x) (((x) & 0x1f) << 10) | ||
518 | #define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5) | ||
519 | #define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0) | ||
520 | |||
521 | |||
522 | #endif /* _AU1000_PSC_H_ */ | ||