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-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_ide.h251
1 files changed, 124 insertions, 127 deletions
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
index b493a5e46c63..60638b8969ba 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_ide.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h
@@ -31,167 +31,164 @@
31 */ 31 */
32 32
33#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA 33#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
34 #define DMA_WAIT_TIMEOUT 100 34#define DMA_WAIT_TIMEOUT 100
35 #define NUM_DESCRIPTORS PRD_ENTRIES 35#define NUM_DESCRIPTORS PRD_ENTRIES
36#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */ 36#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
37 #define NUM_DESCRIPTORS 2 37#define NUM_DESCRIPTORS 2
38#endif 38#endif
39 39
40#ifndef AU1XXX_ATA_RQSIZE 40#ifndef AU1XXX_ATA_RQSIZE
41 #define AU1XXX_ATA_RQSIZE 128 41#define AU1XXX_ATA_RQSIZE 128
42#endif 42#endif
43 43
44/* Disable Burstable-Support for DBDMA */ 44/* Disable Burstable-Support for DBDMA */
45#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 45#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
46 #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0 46#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
47#endif 47#endif
48 48
49#ifdef CONFIG_PM 49#ifdef CONFIG_PM
50/* 50/*
51* This will enable the device to be powered up when write() or read() 51 * This will enable the device to be powered up when write() or read()
52* is called. If this is not defined, the driver will return -EBUSY. 52 * is called. If this is not defined, the driver will return -EBUSY.
53*/ 53 */
54#define WAKE_ON_ACCESS 1 54#define WAKE_ON_ACCESS 1
55 55
56typedef struct 56typedef struct {
57{ 57 spinlock_t lock; /* Used to block on state transitions */
58 spinlock_t lock; /* Used to block on state transitions */ 58 au1xxx_power_dev_t *dev; /* Power Managers device structure */
59 au1xxx_power_dev_t *dev; /* Power Managers device structure */ 59 unsigned stopped; /* Used to signal device is stopped */
60 unsigned stopped; /* USed to signaling device is stopped */
61} pm_state; 60} pm_state;
62#endif 61#endif
63 62
64 63typedef struct {
65typedef struct 64 u32 tx_dev_id, rx_dev_id, target_dev_id;
66{ 65 u32 tx_chan, rx_chan;
67 u32 tx_dev_id, rx_dev_id, target_dev_id; 66 void *tx_desc_head, *rx_desc_head;
68 u32 tx_chan, rx_chan; 67 ide_hwif_t *hwif;
69 void *tx_desc_head, *rx_desc_head;
70 ide_hwif_t *hwif;
71#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA 68#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
72 ide_drive_t *drive; 69 ide_drive_t *drive;
73 struct dbdma_cmd *dma_table_cpu; 70 struct dbdma_cmd *dma_table_cpu;
74 dma_addr_t dma_table_dma; 71 dma_addr_t dma_table_dma;
75#endif 72#endif
76 int irq; 73 int irq;
77 u32 regbase; 74 u32 regbase;
78#ifdef CONFIG_PM 75#ifdef CONFIG_PM
79 pm_state pm; 76 pm_state pm;
80#endif 77#endif
81} _auide_hwif; 78} _auide_hwif;
82 79
83/******************************************************************************* 80/******************************************************************************/
84* PIO Mode timing calculation : * 81/* PIO Mode timing calculation : */
85* * 82/* */
86* Static Bus Spec ATA Spec * 83/* Static Bus Spec ATA Spec */
87* Tcsoe = t1 * 84/* Tcsoe = t1 */
88* Toecs = t9 * 85/* Toecs = t9 */
89* Twcs = t9 * 86/* Twcs = t9 */
90* Tcsh = t2i | t2 * 87/* Tcsh = t2i | t2 */
91* Tcsoff = t2i | t2 * 88/* Tcsoff = t2i | t2 */
92* Twp = t2 * 89/* Twp = t2 */
93* Tcsw = t1 * 90/* Tcsw = t1 */
94* Tpm = 0 * 91/* Tpm = 0 */
95* Ta = t1+t2 * 92/* Ta = t1+t2 */
96*******************************************************************************/ 93/******************************************************************************/
97 94
98#define TCSOE_MASK (0x07<<29) 95#define TCSOE_MASK (0x07 << 29)
99#define TOECS_MASK (0x07<<26) 96#define TOECS_MASK (0x07 << 26)
100#define TWCS_MASK (0x07<<28) 97#define TWCS_MASK (0x07 << 28)
101#define TCSH_MASK (0x0F<<24) 98#define TCSH_MASK (0x0F << 24)
102#define TCSOFF_MASK (0x07<<20) 99#define TCSOFF_MASK (0x07 << 20)
103#define TWP_MASK (0x3F<<14) 100#define TWP_MASK (0x3F << 14)
104#define TCSW_MASK (0x0F<<10) 101#define TCSW_MASK (0x0F << 10)
105#define TPM_MASK (0x0F<<6) 102#define TPM_MASK (0x0F << 6)
106#define TA_MASK (0x3F<<0) 103#define TA_MASK (0x3F << 0)
107#define TS_MASK (1<<8) 104#define TS_MASK (1 << 8)
108 105
109/* Timing parameters PIO mode 0 */ 106/* Timing parameters PIO mode 0 */
110#define SBC_IDE_PIO0_TCSOE (0x04<<29) 107#define SBC_IDE_PIO0_TCSOE (0x04 << 29)
111#define SBC_IDE_PIO0_TOECS (0x01<<26) 108#define SBC_IDE_PIO0_TOECS (0x01 << 26)
112#define SBC_IDE_PIO0_TWCS (0x02<<28) 109#define SBC_IDE_PIO0_TWCS (0x02 << 28)
113#define SBC_IDE_PIO0_TCSH (0x08<<24) 110#define SBC_IDE_PIO0_TCSH (0x08 << 24)
114#define SBC_IDE_PIO0_TCSOFF (0x07<<20) 111#define SBC_IDE_PIO0_TCSOFF (0x07 << 20)
115#define SBC_IDE_PIO0_TWP (0x10<<14) 112#define SBC_IDE_PIO0_TWP (0x10 << 14)
116#define SBC_IDE_PIO0_TCSW (0x04<<10) 113#define SBC_IDE_PIO0_TCSW (0x04 << 10)
117#define SBC_IDE_PIO0_TPM (0x0<<6) 114#define SBC_IDE_PIO0_TPM (0x00 << 6)
118#define SBC_IDE_PIO0_TA (0x15<<0) 115#define SBC_IDE_PIO0_TA (0x15 << 0)
119/* Timing parameters PIO mode 1 */ 116/* Timing parameters PIO mode 1 */
120#define SBC_IDE_PIO1_TCSOE (0x03<<29) 117#define SBC_IDE_PIO1_TCSOE (0x03 << 29)
121#define SBC_IDE_PIO1_TOECS (0x01<<26) 118#define SBC_IDE_PIO1_TOECS (0x01 << 26)
122#define SBC_IDE_PIO1_TWCS (0x01<<28) 119#define SBC_IDE_PIO1_TWCS (0x01 << 28)
123#define SBC_IDE_PIO1_TCSH (0x06<<24) 120#define SBC_IDE_PIO1_TCSH (0x06 << 24)
124#define SBC_IDE_PIO1_TCSOFF (0x06<<20) 121#define SBC_IDE_PIO1_TCSOFF (0x06 << 20)
125#define SBC_IDE_PIO1_TWP (0x08<<14) 122#define SBC_IDE_PIO1_TWP (0x08 << 14)
126#define SBC_IDE_PIO1_TCSW (0x03<<10) 123#define SBC_IDE_PIO1_TCSW (0x03 << 10)
127#define SBC_IDE_PIO1_TPM (0x00<<6) 124#define SBC_IDE_PIO1_TPM (0x00 << 6)
128#define SBC_IDE_PIO1_TA (0x0B<<0) 125#define SBC_IDE_PIO1_TA (0x0B << 0)
129/* Timing parameters PIO mode 2 */ 126/* Timing parameters PIO mode 2 */
130#define SBC_IDE_PIO2_TCSOE (0x05<<29) 127#define SBC_IDE_PIO2_TCSOE (0x05 << 29)
131#define SBC_IDE_PIO2_TOECS (0x01<<26) 128#define SBC_IDE_PIO2_TOECS (0x01 << 26)
132#define SBC_IDE_PIO2_TWCS (0x01<<28) 129#define SBC_IDE_PIO2_TWCS (0x01 << 28)
133#define SBC_IDE_PIO2_TCSH (0x07<<24) 130#define SBC_IDE_PIO2_TCSH (0x07 << 24)
134#define SBC_IDE_PIO2_TCSOFF (0x07<<20) 131#define SBC_IDE_PIO2_TCSOFF (0x07 << 20)
135#define SBC_IDE_PIO2_TWP (0x1F<<14) 132#define SBC_IDE_PIO2_TWP (0x1F << 14)
136#define SBC_IDE_PIO2_TCSW (0x05<<10) 133#define SBC_IDE_PIO2_TCSW (0x05 << 10)
137#define SBC_IDE_PIO2_TPM (0x00<<6) 134#define SBC_IDE_PIO2_TPM (0x00 << 6)
138#define SBC_IDE_PIO2_TA (0x22<<0) 135#define SBC_IDE_PIO2_TA (0x22 << 0)
139/* Timing parameters PIO mode 3 */ 136/* Timing parameters PIO mode 3 */
140#define SBC_IDE_PIO3_TCSOE (0x05<<29) 137#define SBC_IDE_PIO3_TCSOE (0x05 << 29)
141#define SBC_IDE_PIO3_TOECS (0x01<<26) 138#define SBC_IDE_PIO3_TOECS (0x01 << 26)
142#define SBC_IDE_PIO3_TWCS (0x01<<28) 139#define SBC_IDE_PIO3_TWCS (0x01 << 28)
143#define SBC_IDE_PIO3_TCSH (0x0D<<24) 140#define SBC_IDE_PIO3_TCSH (0x0D << 24)
144#define SBC_IDE_PIO3_TCSOFF (0x0D<<20) 141#define SBC_IDE_PIO3_TCSOFF (0x0D << 20)
145#define SBC_IDE_PIO3_TWP (0x15<<14) 142#define SBC_IDE_PIO3_TWP (0x15 << 14)
146#define SBC_IDE_PIO3_TCSW (0x05<<10) 143#define SBC_IDE_PIO3_TCSW (0x05 << 10)
147#define SBC_IDE_PIO3_TPM (0x00<<6) 144#define SBC_IDE_PIO3_TPM (0x00 << 6)
148#define SBC_IDE_PIO3_TA (0x1A<<0) 145#define SBC_IDE_PIO3_TA (0x1A << 0)
149/* Timing parameters PIO mode 4 */ 146/* Timing parameters PIO mode 4 */
150#define SBC_IDE_PIO4_TCSOE (0x04<<29) 147#define SBC_IDE_PIO4_TCSOE (0x04 << 29)
151#define SBC_IDE_PIO4_TOECS (0x01<<26) 148#define SBC_IDE_PIO4_TOECS (0x01 << 26)
152#define SBC_IDE_PIO4_TWCS (0x01<<28) 149#define SBC_IDE_PIO4_TWCS (0x01 << 28)
153#define SBC_IDE_PIO4_TCSH (0x04<<24) 150#define SBC_IDE_PIO4_TCSH (0x04 << 24)
154#define SBC_IDE_PIO4_TCSOFF (0x04<<20) 151#define SBC_IDE_PIO4_TCSOFF (0x04 << 20)
155#define SBC_IDE_PIO4_TWP (0x0D<<14) 152#define SBC_IDE_PIO4_TWP (0x0D << 14)
156#define SBC_IDE_PIO4_TCSW (0x03<<10) 153#define SBC_IDE_PIO4_TCSW (0x03 << 10)
157#define SBC_IDE_PIO4_TPM (0x00<<6) 154#define SBC_IDE_PIO4_TPM (0x00 << 6)
158#define SBC_IDE_PIO4_TA (0x12<<0) 155#define SBC_IDE_PIO4_TA (0x12 << 0)
159/* Timing parameters MDMA mode 0 */ 156/* Timing parameters MDMA mode 0 */
160#define SBC_IDE_MDMA0_TCSOE (0x03<<29) 157#define SBC_IDE_MDMA0_TCSOE (0x03 << 29)
161#define SBC_IDE_MDMA0_TOECS (0x01<<26) 158#define SBC_IDE_MDMA0_TOECS (0x01 << 26)
162#define SBC_IDE_MDMA0_TWCS (0x01<<28) 159#define SBC_IDE_MDMA0_TWCS (0x01 << 28)
163#define SBC_IDE_MDMA0_TCSH (0x07<<24) 160#define SBC_IDE_MDMA0_TCSH (0x07 << 24)
164#define SBC_IDE_MDMA0_TCSOFF (0x07<<20) 161#define SBC_IDE_MDMA0_TCSOFF (0x07 << 20)
165#define SBC_IDE_MDMA0_TWP (0x0C<<14) 162#define SBC_IDE_MDMA0_TWP (0x0C << 14)
166#define SBC_IDE_MDMA0_TCSW (0x03<<10) 163#define SBC_IDE_MDMA0_TCSW (0x03 << 10)
167#define SBC_IDE_MDMA0_TPM (0x00<<6) 164#define SBC_IDE_MDMA0_TPM (0x00 << 6)
168#define SBC_IDE_MDMA0_TA (0x0F<<0) 165#define SBC_IDE_MDMA0_TA (0x0F << 0)
169/* Timing parameters MDMA mode 1 */ 166/* Timing parameters MDMA mode 1 */
170#define SBC_IDE_MDMA1_TCSOE (0x05<<29) 167#define SBC_IDE_MDMA1_TCSOE (0x05 << 29)
171#define SBC_IDE_MDMA1_TOECS (0x01<<26) 168#define SBC_IDE_MDMA1_TOECS (0x01 << 26)
172#define SBC_IDE_MDMA1_TWCS (0x01<<28) 169#define SBC_IDE_MDMA1_TWCS (0x01 << 28)
173#define SBC_IDE_MDMA1_TCSH (0x05<<24) 170#define SBC_IDE_MDMA1_TCSH (0x05 << 24)
174#define SBC_IDE_MDMA1_TCSOFF (0x05<<20) 171#define SBC_IDE_MDMA1_TCSOFF (0x05 << 20)
175#define SBC_IDE_MDMA1_TWP (0x0F<<14) 172#define SBC_IDE_MDMA1_TWP (0x0F << 14)
176#define SBC_IDE_MDMA1_TCSW (0x05<<10) 173#define SBC_IDE_MDMA1_TCSW (0x05 << 10)
177#define SBC_IDE_MDMA1_TPM (0x00<<6) 174#define SBC_IDE_MDMA1_TPM (0x00 << 6)
178#define SBC_IDE_MDMA1_TA (0x15<<0) 175#define SBC_IDE_MDMA1_TA (0x15 << 0)
179/* Timing parameters MDMA mode 2 */ 176/* Timing parameters MDMA mode 2 */
180#define SBC_IDE_MDMA2_TCSOE (0x04<<29) 177#define SBC_IDE_MDMA2_TCSOE (0x04 << 29)
181#define SBC_IDE_MDMA2_TOECS (0x01<<26) 178#define SBC_IDE_MDMA2_TOECS (0x01 << 26)
182#define SBC_IDE_MDMA2_TWCS (0x01<<28) 179#define SBC_IDE_MDMA2_TWCS (0x01 << 28)
183#define SBC_IDE_MDMA2_TCSH (0x04<<24) 180#define SBC_IDE_MDMA2_TCSH (0x04 << 24)
184#define SBC_IDE_MDMA2_TCSOFF (0x04<<20) 181#define SBC_IDE_MDMA2_TCSOFF (0x04 << 20)
185#define SBC_IDE_MDMA2_TWP (0x0D<<14) 182#define SBC_IDE_MDMA2_TWP (0x0D << 14)
186#define SBC_IDE_MDMA2_TCSW (0x04<<10) 183#define SBC_IDE_MDMA2_TCSW (0x04 << 10)
187#define SBC_IDE_MDMA2_TPM (0x00<<6) 184#define SBC_IDE_MDMA2_TPM (0x00 << 6)
188#define SBC_IDE_MDMA2_TA (0x12<<0) 185#define SBC_IDE_MDMA2_TA (0x12 << 0)
189 186
190#define SBC_IDE_TIMING(mode) \ 187#define SBC_IDE_TIMING(mode) \
191 SBC_IDE_##mode##_TWCS | \ 188 (SBC_IDE_##mode##_TWCS | \
192 SBC_IDE_##mode##_TCSH | \ 189 SBC_IDE_##mode##_TCSH | \
193 SBC_IDE_##mode##_TCSOFF | \ 190 SBC_IDE_##mode##_TCSOFF | \
194 SBC_IDE_##mode##_TWP | \ 191 SBC_IDE_##mode##_TWP | \
195 SBC_IDE_##mode##_TCSW | \ 192 SBC_IDE_##mode##_TCSW | \
196 SBC_IDE_##mode##_TPM | \ 193 SBC_IDE_##mode##_TPM | \
197 SBC_IDE_##mode##_TA 194 SBC_IDE_##mode##_TA)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 22:56:21 -0500