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Diffstat (limited to 'include/asm-mips/mach-au1x00/au1xxx_dbdma.h')
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_dbdma.h128
1 files changed, 111 insertions, 17 deletions
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
index d5eb88cd7d51..b327bcd3fee1 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
@@ -45,7 +45,7 @@
45#define DDMA_GLOBAL_BASE 0xb4003000 45#define DDMA_GLOBAL_BASE 0xb4003000
46#define DDMA_CHANNEL_BASE 0xb4002000 46#define DDMA_CHANNEL_BASE 0xb4002000
47 47
48typedef struct dbdma_global { 48typedef volatile struct dbdma_global {
49 u32 ddma_config; 49 u32 ddma_config;
50 u32 ddma_intstat; 50 u32 ddma_intstat;
51 u32 ddma_throttle; 51 u32 ddma_throttle;
@@ -62,7 +62,7 @@ typedef struct dbdma_global {
62 62
63/* The structure of a DMA Channel. 63/* The structure of a DMA Channel.
64*/ 64*/
65typedef struct au1xxx_dma_channel { 65typedef volatile struct au1xxx_dma_channel {
66 u32 ddma_cfg; /* See below */ 66 u32 ddma_cfg; /* See below */
67 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */ 67 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
68 u32 ddma_statptr; /* word aligned pointer to status word */ 68 u32 ddma_statptr; /* word aligned pointer to status word */
@@ -98,7 +98,7 @@ typedef struct au1xxx_dma_channel {
98/* "Standard" DDMA Descriptor. 98/* "Standard" DDMA Descriptor.
99 * Must be 32-byte aligned. 99 * Must be 32-byte aligned.
100 */ 100 */
101typedef struct au1xxx_ddma_desc { 101typedef volatile struct au1xxx_ddma_desc {
102 u32 dscr_cmd0; /* See below */ 102 u32 dscr_cmd0; /* See below */
103 u32 dscr_cmd1; /* See below */ 103 u32 dscr_cmd1; /* See below */
104 u32 dscr_source0; /* source phys address */ 104 u32 dscr_source0; /* source phys address */
@@ -107,6 +107,12 @@ typedef struct au1xxx_ddma_desc {
107 u32 dscr_dest1; /* See below */ 107 u32 dscr_dest1; /* See below */
108 u32 dscr_stat; /* completion status */ 108 u32 dscr_stat; /* completion status */
109 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ 109 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
110 /* First 32bytes are HW specific!!!
111 Lets have some SW data following.. make sure its 32bytes
112 */
113 u32 sw_status;
114 u32 sw_context;
115 u32 sw_reserved[6];
110} au1x_ddma_desc_t; 116} au1x_ddma_desc_t;
111 117
112#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */ 118#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */
@@ -125,8 +131,11 @@ typedef struct au1xxx_ddma_desc {
125#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */ 131#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
126#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ 132#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
127 133
134#define SW_STATUS_INUSE (1<<0)
135
128/* Command 0 device IDs. 136/* Command 0 device IDs.
129*/ 137*/
138#ifdef CONFIG_SOC_AU1550
130#define DSCR_CMD0_UART0_TX 0 139#define DSCR_CMD0_UART0_TX 0
131#define DSCR_CMD0_UART0_RX 1 140#define DSCR_CMD0_UART0_RX 1
132#define DSCR_CMD0_UART3_TX 2 141#define DSCR_CMD0_UART3_TX 2
@@ -155,9 +164,45 @@ typedef struct au1xxx_ddma_desc {
155#define DSCR_CMD0_MAC0_TX 25 164#define DSCR_CMD0_MAC0_TX 25
156#define DSCR_CMD0_MAC1_RX 26 165#define DSCR_CMD0_MAC1_RX 26
157#define DSCR_CMD0_MAC1_TX 27 166#define DSCR_CMD0_MAC1_TX 27
167#endif /* CONFIG_SOC_AU1550 */
168
169#ifdef CONFIG_SOC_AU1200
170#define DSCR_CMD0_UART0_TX 0
171#define DSCR_CMD0_UART0_RX 1
172#define DSCR_CMD0_UART1_TX 2
173#define DSCR_CMD0_UART1_RX 3
174#define DSCR_CMD0_DMA_REQ0 4
175#define DSCR_CMD0_DMA_REQ1 5
176#define DSCR_CMD0_MAE_BE 6
177#define DSCR_CMD0_MAE_FE 7
178#define DSCR_CMD0_SDMS_TX0 8
179#define DSCR_CMD0_SDMS_RX0 9
180#define DSCR_CMD0_SDMS_TX1 10
181#define DSCR_CMD0_SDMS_RX1 11
182#define DSCR_CMD0_AES_TX 13
183#define DSCR_CMD0_AES_RX 12
184#define DSCR_CMD0_PSC0_TX 14
185#define DSCR_CMD0_PSC0_RX 15
186#define DSCR_CMD0_PSC1_TX 16
187#define DSCR_CMD0_PSC1_RX 17
188#define DSCR_CMD0_CIM_RXA 18
189#define DSCR_CMD0_CIM_RXB 19
190#define DSCR_CMD0_CIM_RXC 20
191#define DSCR_CMD0_MAE_BOTH 21
192#define DSCR_CMD0_LCD 22
193#define DSCR_CMD0_NAND_FLASH 23
194#define DSCR_CMD0_PSC0_SYNC 24
195#define DSCR_CMD0_PSC1_SYNC 25
196#define DSCR_CMD0_CIM_SYNC 26
197#endif /* CONFIG_SOC_AU1200 */
198
158#define DSCR_CMD0_THROTTLE 30 199#define DSCR_CMD0_THROTTLE 30
159#define DSCR_CMD0_ALWAYS 31 200#define DSCR_CMD0_ALWAYS 31
160#define DSCR_NDEV_IDS 32 201#define DSCR_NDEV_IDS 32
202/* THis macro is used to find/create custom device types */
203#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
204#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF)
205
161 206
162#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25) 207#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
163#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20) 208#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
@@ -246,6 +291,43 @@ typedef struct au1xxx_ddma_desc {
246*/ 291*/
247#define NUM_DBDMA_CHANS 16 292#define NUM_DBDMA_CHANS 16
248 293
294/*
295 * Ddma API definitions
296 * FIXME: may not fit to this header file
297 */
298typedef struct dbdma_device_table {
299 u32 dev_id;
300 u32 dev_flags;
301 u32 dev_tsize;
302 u32 dev_devwidth;
303 u32 dev_physaddr; /* If FIFO */
304 u32 dev_intlevel;
305 u32 dev_intpolarity;
306} dbdev_tab_t;
307
308
309typedef struct dbdma_chan_config {
310 spinlock_t lock;
311
312 u32 chan_flags;
313 u32 chan_index;
314 dbdev_tab_t *chan_src;
315 dbdev_tab_t *chan_dest;
316 au1x_dma_chan_t *chan_ptr;
317 au1x_ddma_desc_t *chan_desc_base;
318 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
319 void *chan_callparam;
320 void (*chan_callback)(int, void *, struct pt_regs *);
321} chan_tab_t;
322
323#define DEV_FLAGS_INUSE (1 << 0)
324#define DEV_FLAGS_ANYUSE (1 << 1)
325#define DEV_FLAGS_OUT (1 << 2)
326#define DEV_FLAGS_IN (1 << 3)
327#define DEV_FLAGS_BURSTABLE (1 << 4)
328#define DEV_FLAGS_SYNC (1 << 5)
329/* end Ddma API definitions */
330
249/* External functions for drivers to use. 331/* External functions for drivers to use.
250*/ 332*/
251/* Use this to allocate a dbdma channel. The device ids are one of the 333/* Use this to allocate a dbdma channel. The device ids are one of the
@@ -258,18 +340,6 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
258 340
259#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS 341#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
260 342
261/* ACK! These should be in a board specific description file.
262*/
263#ifdef CONFIG_MIPS_PB1550
264#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
265#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
266#endif
267#ifdef CONFIG_MIPS_DB1550
268#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
269#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
270#endif
271
272
273/* Set the device width of a in/out fifo. 343/* Set the device width of a in/out fifo.
274*/ 344*/
275u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); 345u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
@@ -280,8 +350,8 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
280 350
281/* Put buffers on source/destination descriptors. 351/* Put buffers on source/destination descriptors.
282*/ 352*/
283u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes); 353u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
284u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes); 354u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
285 355
286/* Get a buffer from the destination descriptor. 356/* Get a buffer from the destination descriptor.
287*/ 357*/
@@ -295,5 +365,29 @@ u32 au1xxx_get_dma_residue(u32 chanid);
295void au1xxx_dbdma_chan_free(u32 chanid); 365void au1xxx_dbdma_chan_free(u32 chanid);
296void au1xxx_dbdma_dump(u32 chanid); 366void au1xxx_dbdma_dump(u32 chanid);
297 367
368u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
369
370u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
371void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
372
373/*
374 Some compatibilty macros --
375 Needed to make changes to API without breaking existing drivers
376*/
377#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
378#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
379#define put_source_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags)
380
381
382#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
383#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
384#define put_dest_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags)
385
386/*
387 * Flags for the put_source/put_dest functions.
388 */
389#define DDMA_FLAGS_IE (1<<0)
390#define DDMA_FLAGS_NOIE (1<<1)
391
298#endif /* _LANGUAGE_ASSEMBLY */ 392#endif /* _LANGUAGE_ASSEMBLY */
299#endif /* _AU1000_DBDMA_H_ */ 393#endif /* _AU1000_DBDMA_H_ */