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-rw-r--r--include/asm-mips/mach-au1x00/au1000.h554
1 files changed, 463 insertions, 91 deletions
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 148bae2fa7d3..8327ec341c18 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -60,59 +60,36 @@ void static inline au_sync_delay(int ms)
60 mdelay(ms); 60 mdelay(ms);
61} 61}
62 62
63void static inline au_writeb(u8 val, int reg) 63void static inline au_writeb(u8 val, unsigned long reg)
64{ 64{
65 *(volatile u8 *)(reg) = val; 65 *(volatile u8 *)(reg) = val;
66} 66}
67 67
68void static inline au_writew(u16 val, int reg) 68void static inline au_writew(u16 val, unsigned long reg)
69{ 69{
70 *(volatile u16 *)(reg) = val; 70 *(volatile u16 *)(reg) = val;
71} 71}
72 72
73void static inline au_writel(u32 val, int reg) 73void static inline au_writel(u32 val, unsigned long reg)
74{ 74{
75 *(volatile u32 *)(reg) = val; 75 *(volatile u32 *)(reg) = val;
76} 76}
77 77
78static inline u8 au_readb(unsigned long port) 78static inline u8 au_readb(unsigned long reg)
79{ 79{
80 return (*(volatile u8 *)port); 80 return (*(volatile u8 *)reg);
81} 81}
82 82
83static inline u16 au_readw(unsigned long port) 83static inline u16 au_readw(unsigned long reg)
84{ 84{
85 return (*(volatile u16 *)port); 85 return (*(volatile u16 *)reg);
86} 86}
87 87
88static inline u32 au_readl(unsigned long port) 88static inline u32 au_readl(unsigned long reg)
89{ 89{
90 return (*(volatile u32 *)port); 90 return (*(volatile u32 *)reg);
91} 91}
92 92
93/* These next three functions should be a generic part of the MIPS
94 * kernel (with the 'au_' removed from the name) and selected for
95 * processors that support the instructions.
96 * Taken from PPC tree. -- Dan
97 */
98/* Return the bit position of the most significant 1 bit in a word */
99static __inline__ int __ilog2(unsigned int x)
100{
101 int lz;
102
103 asm volatile (
104 ".set\tnoreorder\n\t"
105 ".set\tnoat\n\t"
106 ".set\tmips32\n\t"
107 "clz\t%0,%1\n\t"
108 ".set\tmips0\n\t"
109 ".set\tat\n\t"
110 ".set\treorder"
111 : "=r" (lz)
112 : "r" (x));
113
114 return 31 - lz;
115}
116 93
117static __inline__ int au_ffz(unsigned int x) 94static __inline__ int au_ffz(unsigned int x)
118{ 95{
@@ -162,28 +139,293 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
162#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) 139#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
163#endif 140#endif
164 141
165/* SDRAM Controller */ 142/*
143 * SDRAM Register Offsets
144 */
166#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100) 145#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
167#define MEM_SDMODE0 0xB4000000 146#define MEM_SDMODE0 (0x0000)
168#define MEM_SDMODE1 0xB4000004 147#define MEM_SDMODE1 (0x0004)
169#define MEM_SDMODE2 0xB4000008 148#define MEM_SDMODE2 (0x0008)
149#define MEM_SDADDR0 (0x000C)
150#define MEM_SDADDR1 (0x0010)
151#define MEM_SDADDR2 (0x0014)
152#define MEM_SDREFCFG (0x0018)
153#define MEM_SDPRECMD (0x001C)
154#define MEM_SDAUTOREF (0x0020)
155#define MEM_SDWRMD0 (0x0024)
156#define MEM_SDWRMD1 (0x0028)
157#define MEM_SDWRMD2 (0x002C)
158#define MEM_SDSLEEP (0x0030)
159#define MEM_SDSMCKE (0x0034)
170 160
171#define MEM_SDADDR0 0xB400000C 161/*
172#define MEM_SDADDR1 0xB4000010 162 * MEM_SDMODE register content definitions
173#define MEM_SDADDR2 0xB4000014 163 */
164#define MEM_SDMODE_F (1<<22)
165#define MEM_SDMODE_SR (1<<21)
166#define MEM_SDMODE_BS (1<<20)
167#define MEM_SDMODE_RS (3<<18)
168#define MEM_SDMODE_CS (7<<15)
169#define MEM_SDMODE_TRAS (15<<11)
170#define MEM_SDMODE_TMRD (3<<9)
171#define MEM_SDMODE_TWR (3<<7)
172#define MEM_SDMODE_TRP (3<<5)
173#define MEM_SDMODE_TRCD (3<<3)
174#define MEM_SDMODE_TCL (7<<0)
175
176#define MEM_SDMODE_BS_2Bank (0<<20)
177#define MEM_SDMODE_BS_4Bank (1<<20)
178#define MEM_SDMODE_RS_11Row (0<<18)
179#define MEM_SDMODE_RS_12Row (1<<18)
180#define MEM_SDMODE_RS_13Row (2<<18)
181#define MEM_SDMODE_RS_N(N) ((N)<<18)
182#define MEM_SDMODE_CS_7Col (0<<15)
183#define MEM_SDMODE_CS_8Col (1<<15)
184#define MEM_SDMODE_CS_9Col (2<<15)
185#define MEM_SDMODE_CS_10Col (3<<15)
186#define MEM_SDMODE_CS_11Col (4<<15)
187#define MEM_SDMODE_CS_N(N) ((N)<<15)
188#define MEM_SDMODE_TRAS_N(N) ((N)<<11)
189#define MEM_SDMODE_TMRD_N(N) ((N)<<9)
190#define MEM_SDMODE_TWR_N(N) ((N)<<7)
191#define MEM_SDMODE_TRP_N(N) ((N)<<5)
192#define MEM_SDMODE_TRCD_N(N) ((N)<<3)
193#define MEM_SDMODE_TCL_N(N) ((N)<<0)
174 194
175#define MEM_SDREFCFG 0xB4000018 195/*
176#define MEM_SDPRECMD 0xB400001C 196 * MEM_SDADDR register contents definitions
177#define MEM_SDAUTOREF 0xB4000020 197 */
198#define MEM_SDADDR_E (1<<20)
199#define MEM_SDADDR_CSBA (0x03FF<<10)
200#define MEM_SDADDR_CSMASK (0x03FF<<0)
201#define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12)
202#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22)
203
204/*
205 * MEM_SDREFCFG register content definitions
206 */
207#define MEM_SDREFCFG_TRC (15<<28)
208#define MEM_SDREFCFG_TRPM (3<<26)
209#define MEM_SDREFCFG_E (1<<25)
210#define MEM_SDREFCFG_RE (0x1ffffff<<0)
211#define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC)
212#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM)
213#define MEM_SDREFCFG_REF_N(N) (N)
214#endif
178 215
179#define MEM_SDWRMD0 0xB4000024 216/***********************************************************************/
180#define MEM_SDWRMD1 0xB4000028
181#define MEM_SDWRMD2 0xB400002C
182 217
183#define MEM_SDSLEEP 0xB4000030 218/*
184#define MEM_SDSMCKE 0xB4000034 219 * Au1550 SDRAM Register Offsets
220 */
221
222/***********************************************************************/
223
224#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
225#define MEM_SDMODE0 (0x0800)
226#define MEM_SDMODE1 (0x0808)
227#define MEM_SDMODE2 (0x0810)
228#define MEM_SDADDR0 (0x0820)
229#define MEM_SDADDR1 (0x0828)
230#define MEM_SDADDR2 (0x0830)
231#define MEM_SDCONFIGA (0x0840)
232#define MEM_SDCONFIGB (0x0848)
233#define MEM_SDSTAT (0x0850)
234#define MEM_SDERRADDR (0x0858)
235#define MEM_SDSTRIDE0 (0x0860)
236#define MEM_SDSTRIDE1 (0x0868)
237#define MEM_SDSTRIDE2 (0x0870)
238#define MEM_SDWRMD0 (0x0880)
239#define MEM_SDWRMD1 (0x0888)
240#define MEM_SDWRMD2 (0x0890)
241#define MEM_SDPRECMD (0x08C0)
242#define MEM_SDAUTOREF (0x08C8)
243#define MEM_SDSREF (0x08D0)
244#define MEM_SDSLEEP MEM_SDSREF
245
246#endif
247
248/*
249 * Physical base addresses for integrated peripherals
250 */
251
252#ifdef CONFIG_SOC_AU1000
253#define MEM_PHYS_ADDR 0x14000000
254#define STATIC_MEM_PHYS_ADDR 0x14001000
255#define DMA0_PHYS_ADDR 0x14002000
256#define DMA1_PHYS_ADDR 0x14002100
257#define DMA2_PHYS_ADDR 0x14002200
258#define DMA3_PHYS_ADDR 0x14002300
259#define DMA4_PHYS_ADDR 0x14002400
260#define DMA5_PHYS_ADDR 0x14002500
261#define DMA6_PHYS_ADDR 0x14002600
262#define DMA7_PHYS_ADDR 0x14002700
263#define IC0_PHYS_ADDR 0x10400000
264#define IC1_PHYS_ADDR 0x11800000
265#define AC97_PHYS_ADDR 0x10000000
266#define USBH_PHYS_ADDR 0x10100000
267#define USBD_PHYS_ADDR 0x10200000
268#define IRDA_PHYS_ADDR 0x10300000
269#define MAC0_PHYS_ADDR 0x10500000
270#define MAC1_PHYS_ADDR 0x10510000
271#define MACEN_PHYS_ADDR 0x10520000
272#define MACDMA0_PHYS_ADDR 0x14004000
273#define MACDMA1_PHYS_ADDR 0x14004200
274#define I2S_PHYS_ADDR 0x11000000
275#define UART0_PHYS_ADDR 0x11100000
276#define UART1_PHYS_ADDR 0x11200000
277#define UART2_PHYS_ADDR 0x11300000
278#define UART3_PHYS_ADDR 0x11400000
279#define SSI0_PHYS_ADDR 0x11600000
280#define SSI1_PHYS_ADDR 0x11680000
281#define SYS_PHYS_ADDR 0x11900000
282#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
283#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
284#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
185#endif 285#endif
186 286
287/********************************************************************/
288
289#ifdef CONFIG_SOC_AU1500
290#define MEM_PHYS_ADDR 0x14000000
291#define STATIC_MEM_PHYS_ADDR 0x14001000
292#define DMA0_PHYS_ADDR 0x14002000
293#define DMA1_PHYS_ADDR 0x14002100
294#define DMA2_PHYS_ADDR 0x14002200
295#define DMA3_PHYS_ADDR 0x14002300
296#define DMA4_PHYS_ADDR 0x14002400
297#define DMA5_PHYS_ADDR 0x14002500
298#define DMA6_PHYS_ADDR 0x14002600
299#define DMA7_PHYS_ADDR 0x14002700
300#define IC0_PHYS_ADDR 0x10400000
301#define IC1_PHYS_ADDR 0x11800000
302#define AC97_PHYS_ADDR 0x10000000
303#define USBH_PHYS_ADDR 0x10100000
304#define USBD_PHYS_ADDR 0x10200000
305#define PCI_PHYS_ADDR 0x14005000
306#define MAC0_PHYS_ADDR 0x11500000
307#define MAC1_PHYS_ADDR 0x11510000
308#define MACEN_PHYS_ADDR 0x11520000
309#define MACDMA0_PHYS_ADDR 0x14004000
310#define MACDMA1_PHYS_ADDR 0x14004200
311#define I2S_PHYS_ADDR 0x11000000
312#define UART0_PHYS_ADDR 0x11100000
313#define UART3_PHYS_ADDR 0x11400000
314#define GPIO2_PHYS_ADDR 0x11700000
315#define SYS_PHYS_ADDR 0x11900000
316#define PCI_MEM_PHYS_ADDR 0x400000000ULL
317#define PCI_IO_PHYS_ADDR 0x500000000ULL
318#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
319#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
320#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
321#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
322#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
323#endif
324
325/********************************************************************/
326
327#ifdef CONFIG_SOC_AU1100
328#define MEM_PHYS_ADDR 0x14000000
329#define STATIC_MEM_PHYS_ADDR 0x14001000
330#define DMA0_PHYS_ADDR 0x14002000
331#define DMA1_PHYS_ADDR 0x14002100
332#define DMA2_PHYS_ADDR 0x14002200
333#define DMA3_PHYS_ADDR 0x14002300
334#define DMA4_PHYS_ADDR 0x14002400
335#define DMA5_PHYS_ADDR 0x14002500
336#define DMA6_PHYS_ADDR 0x14002600
337#define DMA7_PHYS_ADDR 0x14002700
338#define IC0_PHYS_ADDR 0x10400000
339#define SD0_PHYS_ADDR 0x10600000
340#define SD1_PHYS_ADDR 0x10680000
341#define IC1_PHYS_ADDR 0x11800000
342#define AC97_PHYS_ADDR 0x10000000
343#define USBH_PHYS_ADDR 0x10100000
344#define USBD_PHYS_ADDR 0x10200000
345#define IRDA_PHYS_ADDR 0x10300000
346#define MAC0_PHYS_ADDR 0x10500000
347#define MACEN_PHYS_ADDR 0x10520000
348#define MACDMA0_PHYS_ADDR 0x14004000
349#define MACDMA1_PHYS_ADDR 0x14004200
350#define I2S_PHYS_ADDR 0x11000000
351#define UART0_PHYS_ADDR 0x11100000
352#define UART1_PHYS_ADDR 0x11200000
353#define UART3_PHYS_ADDR 0x11400000
354#define SSI0_PHYS_ADDR 0x11600000
355#define SSI1_PHYS_ADDR 0x11680000
356#define GPIO2_PHYS_ADDR 0x11700000
357#define SYS_PHYS_ADDR 0x11900000
358#define LCD_PHYS_ADDR 0x15000000
359#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
360#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
361#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
362#endif
363
364/***********************************************************************/
365
366#ifdef CONFIG_SOC_AU1550
367#define MEM_PHYS_ADDR 0x14000000
368#define STATIC_MEM_PHYS_ADDR 0x14001000
369#define IC0_PHYS_ADDR 0x10400000
370#define IC1_PHYS_ADDR 0x11800000
371#define USBH_PHYS_ADDR 0x14020000
372#define USBD_PHYS_ADDR 0x10200000
373#define PCI_PHYS_ADDR 0x14005000
374#define MAC0_PHYS_ADDR 0x10500000
375#define MAC1_PHYS_ADDR 0x10510000
376#define MACEN_PHYS_ADDR 0x10520000
377#define MACDMA0_PHYS_ADDR 0x14004000
378#define MACDMA1_PHYS_ADDR 0x14004200
379#define UART0_PHYS_ADDR 0x11100000
380#define UART1_PHYS_ADDR 0x11200000
381#define UART3_PHYS_ADDR 0x11400000
382#define GPIO2_PHYS_ADDR 0x11700000
383#define SYS_PHYS_ADDR 0x11900000
384#define DDMA_PHYS_ADDR 0x14002000
385#define PE_PHYS_ADDR 0x14008000
386#define PSC0_PHYS_ADDR 0x11A00000
387#define PSC1_PHYS_ADDR 0x11B00000
388#define PSC2_PHYS_ADDR 0x10A00000
389#define PSC3_PHYS_ADDR 0x10B00000
390#define PCI_MEM_PHYS_ADDR 0x400000000ULL
391#define PCI_IO_PHYS_ADDR 0x500000000ULL
392#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
393#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
394#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
395#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
396#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
397#endif
398
399/***********************************************************************/
400
401#ifdef CONFIG_SOC_AU1200
402#define MEM_PHYS_ADDR 0x14000000
403#define STATIC_MEM_PHYS_ADDR 0x14001000
404#define AES_PHYS_ADDR 0x10300000
405#define CIM_PHYS_ADDR 0x14004000
406#define IC0_PHYS_ADDR 0x10400000
407#define IC1_PHYS_ADDR 0x11800000
408#define USBM_PHYS_ADDR 0x14020000
409#define USBH_PHYS_ADDR 0x14020100
410#define UART0_PHYS_ADDR 0x11100000
411#define UART1_PHYS_ADDR 0x11200000
412#define GPIO2_PHYS_ADDR 0x11700000
413#define SYS_PHYS_ADDR 0x11900000
414#define DDMA_PHYS_ADDR 0x14002000
415#define PSC0_PHYS_ADDR 0x11A00000
416#define PSC1_PHYS_ADDR 0x11B00000
417#define SD0_PHYS_ADDR 0x10600000
418#define SD1_PHYS_ADDR 0x10680000
419#define LCD_PHYS_ADDR 0x15000000
420#define SWCNT_PHYS_ADDR 0x1110010C
421#define MAEFE_PHYS_ADDR 0x14012000
422#define MAEBE_PHYS_ADDR 0x14010000
423#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
424#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
425#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
426#endif
427
428
187/* Static Bus Controller */ 429/* Static Bus Controller */
188#define MEM_STCFG0 0xB4001000 430#define MEM_STCFG0 0xB4001000
189#define MEM_STTIME0 0xB4001004 431#define MEM_STTIME0 0xB4001004
@@ -369,7 +611,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
369#define AU1000_MAC0_ENABLE 0xB0520000 611#define AU1000_MAC0_ENABLE 0xB0520000
370#define AU1000_MAC1_ENABLE 0xB0520004 612#define AU1000_MAC1_ENABLE 0xB0520004
371#define NUM_ETH_INTERFACES 2 613#define NUM_ETH_INTERFACES 2
372#endif // CONFIG_SOC_AU1000 614#endif /* CONFIG_SOC_AU1000 */
373 615
374/* Au1500 */ 616/* Au1500 */
375#ifdef CONFIG_SOC_AU1500 617#ifdef CONFIG_SOC_AU1500
@@ -429,6 +671,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
429#define AU1500_GPIO_207 62 671#define AU1500_GPIO_207 62
430#define AU1500_GPIO_208_215 63 672#define AU1500_GPIO_208_215 63
431 673
674/* shortcuts */
675#define INTA AU1000_PCI_INTA
676#define INTB AU1000_PCI_INTB
677#define INTC AU1000_PCI_INTC
678#define INTD AU1000_PCI_INTD
679
432#define UART0_ADDR 0xB1100000 680#define UART0_ADDR 0xB1100000
433#define UART3_ADDR 0xB1400000 681#define UART3_ADDR 0xB1400000
434 682
@@ -440,7 +688,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
440#define AU1500_MAC0_ENABLE 0xB1520000 688#define AU1500_MAC0_ENABLE 0xB1520000
441#define AU1500_MAC1_ENABLE 0xB1520004 689#define AU1500_MAC1_ENABLE 0xB1520004
442#define NUM_ETH_INTERFACES 2 690#define NUM_ETH_INTERFACES 2
443#endif // CONFIG_SOC_AU1500 691#endif /* CONFIG_SOC_AU1500 */
444 692
445/* Au1100 */ 693/* Au1100 */
446#ifdef CONFIG_SOC_AU1100 694#ifdef CONFIG_SOC_AU1100
@@ -485,6 +733,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
485#define AU1000_GPIO_13 45 733#define AU1000_GPIO_13 45
486#define AU1000_GPIO_14 46 734#define AU1000_GPIO_14 46
487#define AU1000_GPIO_15 47 735#define AU1000_GPIO_15 47
736#define AU1000_GPIO_16 48
737#define AU1000_GPIO_17 49
738#define AU1000_GPIO_18 50
739#define AU1000_GPIO_19 51
740#define AU1000_GPIO_20 52
741#define AU1000_GPIO_21 53
742#define AU1000_GPIO_22 54
743#define AU1000_GPIO_23 55
744#define AU1000_GPIO_24 56
745#define AU1000_GPIO_25 57
746#define AU1000_GPIO_26 58
747#define AU1000_GPIO_27 59
748#define AU1000_GPIO_28 60
749#define AU1000_GPIO_29 61
750#define AU1000_GPIO_30 62
751#define AU1000_GPIO_31 63
488 752
489#define UART0_ADDR 0xB1100000 753#define UART0_ADDR 0xB1100000
490#define UART1_ADDR 0xB1200000 754#define UART1_ADDR 0xB1200000
@@ -496,7 +760,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
496#define AU1100_ETH0_BASE 0xB0500000 760#define AU1100_ETH0_BASE 0xB0500000
497#define AU1100_MAC0_ENABLE 0xB0520000 761#define AU1100_MAC0_ENABLE 0xB0520000
498#define NUM_ETH_INTERFACES 1 762#define NUM_ETH_INTERFACES 1
499#endif // CONFIG_SOC_AU1100 763#endif /* CONFIG_SOC_AU1100 */
500 764
501#ifdef CONFIG_SOC_AU1550 765#ifdef CONFIG_SOC_AU1550
502#define AU1550_UART0_INT 0 766#define AU1550_UART0_INT 0
@@ -513,14 +777,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
513#define AU1550_PSC1_INT 11 777#define AU1550_PSC1_INT 11
514#define AU1550_PSC2_INT 12 778#define AU1550_PSC2_INT 12
515#define AU1550_PSC3_INT 13 779#define AU1550_PSC3_INT 13
516#define AU1550_TOY_INT 14 780#define AU1000_TOY_INT 14
517#define AU1550_TOY_MATCH0_INT 15 781#define AU1000_TOY_MATCH0_INT 15
518#define AU1550_TOY_MATCH1_INT 16 782#define AU1000_TOY_MATCH1_INT 16
519#define AU1550_TOY_MATCH2_INT 17 783#define AU1000_TOY_MATCH2_INT 17
520#define AU1550_RTC_INT 18 784#define AU1000_RTC_INT 18
521#define AU1550_RTC_MATCH0_INT 19 785#define AU1000_RTC_MATCH0_INT 19
522#define AU1550_RTC_MATCH1_INT 20 786#define AU1000_RTC_MATCH1_INT 20
523#define AU1550_RTC_MATCH2_INT 21 787#define AU1000_RTC_MATCH2_INT 21
524#define AU1550_NAND_INT 23 788#define AU1550_NAND_INT 23
525#define AU1550_USB_DEV_REQ_INT 24 789#define AU1550_USB_DEV_REQ_INT 24
526#define AU1550_USB_DEV_SUS_INT 25 790#define AU1550_USB_DEV_SUS_INT 25
@@ -563,6 +827,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
563#define AU1500_GPIO_207 62 827#define AU1500_GPIO_207 62
564#define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218 828#define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218
565 829
830/* shortcuts */
831#define INTA AU1550_PCI_INTA
832#define INTB AU1550_PCI_INTB
833#define INTC AU1550_PCI_INTC
834#define INTD AU1550_PCI_INTD
835
566#define UART0_ADDR 0xB1100000 836#define UART0_ADDR 0xB1100000
567#define UART1_ADDR 0xB1200000 837#define UART1_ADDR 0xB1200000
568#define UART3_ADDR 0xB1400000 838#define UART3_ADDR 0xB1400000
@@ -575,7 +845,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
575#define AU1550_MAC0_ENABLE 0xB0520000 845#define AU1550_MAC0_ENABLE 0xB0520000
576#define AU1550_MAC1_ENABLE 0xB0520004 846#define AU1550_MAC1_ENABLE 0xB0520004
577#define NUM_ETH_INTERFACES 2 847#define NUM_ETH_INTERFACES 2
578#endif // CONFIG_SOC_AU1550 848#endif /* CONFIG_SOC_AU1550 */
579 849
580#ifdef CONFIG_SOC_AU1200 850#ifdef CONFIG_SOC_AU1200
581#define AU1200_UART0_INT 0 851#define AU1200_UART0_INT 0
@@ -592,14 +862,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
592#define AU1200_PSC1_INT 11 862#define AU1200_PSC1_INT 11
593#define AU1200_AES_INT 12 863#define AU1200_AES_INT 12
594#define AU1200_CAMERA_INT 13 864#define AU1200_CAMERA_INT 13
595#define AU1200_TOY_INT 14 865#define AU1000_TOY_INT 14
596#define AU1200_TOY_MATCH0_INT 15 866#define AU1000_TOY_MATCH0_INT 15
597#define AU1200_TOY_MATCH1_INT 16 867#define AU1000_TOY_MATCH1_INT 16
598#define AU1200_TOY_MATCH2_INT 17 868#define AU1000_TOY_MATCH2_INT 17
599#define AU1200_RTC_INT 18 869#define AU1000_RTC_INT 18
600#define AU1200_RTC_MATCH0_INT 19 870#define AU1000_RTC_MATCH0_INT 19
601#define AU1200_RTC_MATCH1_INT 20 871#define AU1000_RTC_MATCH1_INT 20
602#define AU1200_RTC_MATCH2_INT 21 872#define AU1000_RTC_MATCH2_INT 21
603#define AU1200_NAND_INT 23 873#define AU1200_NAND_INT 23
604#define AU1200_GPIO_204 24 874#define AU1200_GPIO_204 24
605#define AU1200_GPIO_205 25 875#define AU1200_GPIO_205 25
@@ -607,6 +877,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
607#define AU1200_GPIO_207 27 877#define AU1200_GPIO_207 27
608#define AU1200_GPIO_208_215 28 // Logical OR of 208:215 878#define AU1200_GPIO_208_215 28 // Logical OR of 208:215
609#define AU1200_USB_INT 29 879#define AU1200_USB_INT 29
880#define AU1000_USB_HOST_INT AU1200_USB_INT
610#define AU1200_LCD_INT 30 881#define AU1200_LCD_INT 30
611#define AU1200_MAE_BOTH_INT 31 882#define AU1200_MAE_BOTH_INT 31
612#define AU1000_GPIO_0 32 883#define AU1000_GPIO_0 32
@@ -645,20 +916,36 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
645#define UART0_ADDR 0xB1100000 916#define UART0_ADDR 0xB1100000
646#define UART1_ADDR 0xB1200000 917#define UART1_ADDR 0xB1200000
647 918
648#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap 919#define USB_UOC_BASE 0x14020020
649#define USB_HOST_CONFIG 0xB4027ffc 920#define USB_UOC_LEN 0x20
650 921#define USB_OHCI_BASE 0x14020100
651// these are here for prototyping on au1550 (do not exist on au1200) 922#define USB_OHCI_LEN 0x100
652#define AU1200_ETH0_BASE 0xB0500000 923#define USB_EHCI_BASE 0x14020200
653#define AU1200_ETH1_BASE 0xB0510000 924#define USB_EHCI_LEN 0x100
654#define AU1200_MAC0_ENABLE 0xB0520000 925#define USB_UDC_BASE 0x14022000
655#define AU1200_MAC1_ENABLE 0xB0520004 926#define USB_UDC_LEN 0x2000
656#define NUM_ETH_INTERFACES 2 927#define USB_MSR_BASE 0xB4020000
657#endif // CONFIG_SOC_AU1200 928#define USB_MSR_MCFG 4
929#define USBMSRMCFG_OMEMEN 0
930#define USBMSRMCFG_OBMEN 1
931#define USBMSRMCFG_EMEMEN 2
932#define USBMSRMCFG_EBMEN 3
933#define USBMSRMCFG_DMEMEN 4
934#define USBMSRMCFG_DBMEN 5
935#define USBMSRMCFG_GMEMEN 6
936#define USBMSRMCFG_OHCCLKEN 16
937#define USBMSRMCFG_EHCCLKEN 17
938#define USBMSRMCFG_UDCCLKEN 18
939#define USBMSRMCFG_PHYPLLEN 19
940#define USBMSRMCFG_RDCOMB 30
941#define USBMSRMCFG_PFEN 31
942
943#endif /* CONFIG_SOC_AU1200 */
658 944
659#define AU1000_LAST_INTC0_INT 31 945#define AU1000_LAST_INTC0_INT 31
946#define AU1000_LAST_INTC1_INT 63
660#define AU1000_MAX_INTR 63 947#define AU1000_MAX_INTR 63
661 948#define INTX 0xFF /* not valid */
662 949
663/* Programmable Counters 0 and 1 */ 950/* Programmable Counters 0 and 1 */
664#define SYS_BASE 0xB1900000 951#define SYS_BASE 0xB1900000
@@ -730,6 +1017,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
730 #define I2S_CONTROL_D (1<<1) 1017 #define I2S_CONTROL_D (1<<1)
731 #define I2S_CONTROL_CE (1<<0) 1018 #define I2S_CONTROL_CE (1<<0)
732 1019
1020#ifndef CONFIG_SOC_AU1200
1021
733/* USB Host Controller */ 1022/* USB Host Controller */
734#define USB_OHCI_LEN 0x00100000 1023#define USB_OHCI_LEN 0x00100000
735 1024
@@ -775,6 +1064,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
775 #define USBDEV_ENABLE (1<<1) 1064 #define USBDEV_ENABLE (1<<1)
776 #define USBDEV_CE (1<<0) 1065 #define USBDEV_CE (1<<0)
777 1066
1067#endif /* !CONFIG_SOC_AU1200 */
1068
778/* Ethernet Controllers */ 1069/* Ethernet Controllers */
779 1070
780/* 4 byte offsets from AU1000_ETH_BASE */ 1071/* 4 byte offsets from AU1000_ETH_BASE */
@@ -1173,6 +1464,37 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1173 #define SYS_PF_PSC1_S1 (1 << 1) 1464 #define SYS_PF_PSC1_S1 (1 << 1)
1174 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1465 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1175 1466
1467/* Au1200 Only */
1468#ifdef CONFIG_SOC_AU1200
1469#define SYS_PINFUNC_DMA (1<<31)
1470#define SYS_PINFUNC_S0A (1<<30)
1471#define SYS_PINFUNC_S1A (1<<29)
1472#define SYS_PINFUNC_LP0 (1<<28)
1473#define SYS_PINFUNC_LP1 (1<<27)
1474#define SYS_PINFUNC_LD16 (1<<26)
1475#define SYS_PINFUNC_LD8 (1<<25)
1476#define SYS_PINFUNC_LD1 (1<<24)
1477#define SYS_PINFUNC_LD0 (1<<23)
1478#define SYS_PINFUNC_P1A (3<<21)
1479#define SYS_PINFUNC_P1B (1<<20)
1480#define SYS_PINFUNC_FS3 (1<<19)
1481#define SYS_PINFUNC_P0A (3<<17)
1482#define SYS_PINFUNC_CS (1<<16)
1483#define SYS_PINFUNC_CIM (1<<15)
1484#define SYS_PINFUNC_P1C (1<<14)
1485#define SYS_PINFUNC_U1T (1<<12)
1486#define SYS_PINFUNC_U1R (1<<11)
1487#define SYS_PINFUNC_EX1 (1<<10)
1488#define SYS_PINFUNC_EX0 (1<<9)
1489#define SYS_PINFUNC_U0R (1<<8)
1490#define SYS_PINFUNC_MC (1<<7)
1491#define SYS_PINFUNC_S0B (1<<6)
1492#define SYS_PINFUNC_S0C (1<<5)
1493#define SYS_PINFUNC_P0B (1<<4)
1494#define SYS_PINFUNC_U0T (1<<3)
1495#define SYS_PINFUNC_S1B (1<<2)
1496#endif
1497
1176#define SYS_TRIOUTRD 0xB1900100 1498#define SYS_TRIOUTRD 0xB1900100
1177#define SYS_TRIOUTCLR 0xB1900100 1499#define SYS_TRIOUTCLR 0xB1900100
1178#define SYS_OUTPUTRD 0xB1900108 1500#define SYS_OUTPUTRD 0xB1900108
@@ -1239,6 +1561,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1239 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) 1561 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
1240 #define SYS_CS_DI2 (1<<16) 1562 #define SYS_CS_DI2 (1<<16)
1241 #define SYS_CS_CI2 (1<<15) 1563 #define SYS_CS_CI2 (1<<15)
1564#ifdef CONFIG_SOC_AU1100
1565 #define SYS_CS_ML_BIT 7
1566 #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT)
1567 #define SYS_CS_DL (1<<6)
1568 #define SYS_CS_CL (1<<5)
1569#else
1242 #define SYS_CS_MUH_BIT 12 1570 #define SYS_CS_MUH_BIT 12
1243 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) 1571 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
1244 #define SYS_CS_DUH (1<<11) 1572 #define SYS_CS_DUH (1<<11)
@@ -1247,6 +1575,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1247 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) 1575 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
1248 #define SYS_CS_DUD (1<<6) 1576 #define SYS_CS_DUD (1<<6)
1249 #define SYS_CS_CUD (1<<5) 1577 #define SYS_CS_CUD (1<<5)
1578#endif
1250 #define SYS_CS_MIR_BIT 2 1579 #define SYS_CS_MIR_BIT 2
1251 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) 1580 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
1252 #define SYS_CS_DIR (1<<1) 1581 #define SYS_CS_DIR (1<<1)
@@ -1300,7 +1629,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1300#define SD1_XMIT_FIFO 0xB0680000 1629#define SD1_XMIT_FIFO 0xB0680000
1301#define SD1_RECV_FIFO 0xB0680004 1630#define SD1_RECV_FIFO 0xB0680004
1302 1631
1303
1304#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 1632#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1305/* Au1500 PCI Controller */ 1633/* Au1500 PCI Controller */
1306#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr 1634#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
@@ -1363,36 +1691,77 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1363 _ctl_; }) 1691 _ctl_; })
1364 1692
1365 1693
1366#else /* Au1000 and Au1100 */ 1694#else /* Au1000 and Au1100 and Au1200 */
1367 1695
1368/* don't allow any legacy ports probing */ 1696/* don't allow any legacy ports probing */
1369#define IOPORT_RESOURCE_START 0x10000000; 1697#define IOPORT_RESOURCE_START 0x10000000
1370#define IOPORT_RESOURCE_END 0xffffffff 1698#define IOPORT_RESOURCE_END 0xffffffff
1371#define IOMEM_RESOURCE_START 0x10000000 1699#define IOMEM_RESOURCE_START 0x10000000
1372#define IOMEM_RESOURCE_END 0xffffffff 1700#define IOMEM_RESOURCE_END 0xffffffff
1373 1701
1374#ifdef CONFIG_MIPS_PB1000
1375#define PCI_IO_START 0x10000000
1376#define PCI_IO_END 0x1000ffff
1377#define PCI_MEM_START 0x18000000
1378#define PCI_MEM_END 0x18ffffff
1379#define PCI_FIRST_DEVFN 0
1380#define PCI_LAST_DEVFN 1
1381#else
1382/* no PCI bus controller */
1383#define PCI_IO_START 0 1702#define PCI_IO_START 0
1384#define PCI_IO_END 0 1703#define PCI_IO_END 0
1385#define PCI_MEM_START 0 1704#define PCI_MEM_START 0
1386#define PCI_MEM_END 0 1705#define PCI_MEM_END 0
1387#define PCI_FIRST_DEVFN 0 1706#define PCI_FIRST_DEVFN 0
1388#define PCI_LAST_DEVFN 0 1707#define PCI_LAST_DEVFN 0
1389#endif
1390 1708
1391#endif 1709#endif
1392 1710
1711#ifndef _LANGUAGE_ASSEMBLY
1712typedef volatile struct
1713{
1714 /* 0x0000 */ u32 toytrim;
1715 /* 0x0004 */ u32 toywrite;
1716 /* 0x0008 */ u32 toymatch0;
1717 /* 0x000C */ u32 toymatch1;
1718 /* 0x0010 */ u32 toymatch2;
1719 /* 0x0014 */ u32 cntrctrl;
1720 /* 0x0018 */ u32 scratch0;
1721 /* 0x001C */ u32 scratch1;
1722 /* 0x0020 */ u32 freqctrl0;
1723 /* 0x0024 */ u32 freqctrl1;
1724 /* 0x0028 */ u32 clksrc;
1725 /* 0x002C */ u32 pinfunc;
1726 /* 0x0030 */ u32 reserved0;
1727 /* 0x0034 */ u32 wakemsk;
1728 /* 0x0038 */ u32 endian;
1729 /* 0x003C */ u32 powerctrl;
1730 /* 0x0040 */ u32 toyread;
1731 /* 0x0044 */ u32 rtctrim;
1732 /* 0x0048 */ u32 rtcwrite;
1733 /* 0x004C */ u32 rtcmatch0;
1734 /* 0x0050 */ u32 rtcmatch1;
1735 /* 0x0054 */ u32 rtcmatch2;
1736 /* 0x0058 */ u32 rtcread;
1737 /* 0x005C */ u32 wakesrc;
1738 /* 0x0060 */ u32 cpupll;
1739 /* 0x0064 */ u32 auxpll;
1740 /* 0x0068 */ u32 reserved1;
1741 /* 0x006C */ u32 reserved2;
1742 /* 0x0070 */ u32 reserved3;
1743 /* 0x0074 */ u32 reserved4;
1744 /* 0x0078 */ u32 slppwr;
1745 /* 0x007C */ u32 sleep;
1746 /* 0x0080 */ u32 reserved5[32];
1747 /* 0x0100 */ u32 trioutrd;
1748#define trioutclr trioutrd
1749 /* 0x0104 */ u32 reserved6;
1750 /* 0x0108 */ u32 outputrd;
1751#define outputset outputrd
1752 /* 0x010C */ u32 outputclr;
1753 /* 0x0110 */ u32 pinstaterd;
1754#define pininputen pinstaterd
1755
1756} AU1X00_SYS;
1757
1758static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE;
1759
1760#endif
1393/* Processor information base on prid. 1761/* Processor information base on prid.
1394 * Copied from PowerPC. 1762 * Copied from PowerPC.
1395 */ 1763 */
1764#ifndef _LANGUAGE_ASSEMBLY
1396struct cpu_spec { 1765struct cpu_spec {
1397 /* CPU is matched via (PRID & prid_mask) == prid_value */ 1766 /* CPU is matched via (PRID & prid_mask) == prid_value */
1398 unsigned int prid_mask; 1767 unsigned int prid_mask;
@@ -1406,3 +1775,6 @@ struct cpu_spec {
1406extern struct cpu_spec cpu_specs[]; 1775extern struct cpu_spec cpu_specs[];
1407extern struct cpu_spec *cur_cpu_spec[]; 1776extern struct cpu_spec *cur_cpu_spec[];
1408#endif 1777#endif
1778
1779#endif
1780
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