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-rw-r--r--include/asm-mips/mach-au1x00/au1000.h1644
1 files changed, 820 insertions, 824 deletions
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index a05555165d05..363a14ee0ae5 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -40,8 +40,8 @@
40#include <linux/delay.h> 40#include <linux/delay.h>
41#include <linux/types.h> 41#include <linux/types.h>
42 42
43#include <asm/io.h> 43#include <linux/io.h>
44#include <asm/irq.h> 44#include <linux/irq.h>
45 45
46/* cpu pipeline flush */ 46/* cpu pipeline flush */
47void static inline au_sync(void) 47void static inline au_sync(void)
@@ -63,32 +63,32 @@ void static inline au_sync_delay(int ms)
63 63
64void static inline au_writeb(u8 val, unsigned long reg) 64void static inline au_writeb(u8 val, unsigned long reg)
65{ 65{
66 *(volatile u8 *)(reg) = val; 66 *(volatile u8 *)reg = val;
67} 67}
68 68
69void static inline au_writew(u16 val, unsigned long reg) 69void static inline au_writew(u16 val, unsigned long reg)
70{ 70{
71 *(volatile u16 *)(reg) = val; 71 *(volatile u16 *)reg = val;
72} 72}
73 73
74void static inline au_writel(u32 val, unsigned long reg) 74void static inline au_writel(u32 val, unsigned long reg)
75{ 75{
76 *(volatile u32 *)(reg) = val; 76 *(volatile u32 *)reg = val;
77} 77}
78 78
79static inline u8 au_readb(unsigned long reg) 79static inline u8 au_readb(unsigned long reg)
80{ 80{
81 return (*(volatile u8 *)reg); 81 return *(volatile u8 *)reg;
82} 82}
83 83
84static inline u16 au_readw(unsigned long reg) 84static inline u16 au_readw(unsigned long reg)
85{ 85{
86 return (*(volatile u16 *)reg); 86 return *(volatile u16 *)reg;
87} 87}
88 88
89static inline u32 au_readl(unsigned long reg) 89static inline u32 au_readl(unsigned long reg)
90{ 90{
91 return (*(volatile u32 *)reg); 91 return *(volatile u32 *)reg;
92} 92}
93 93
94 94
@@ -117,76 +117,77 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
117#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 117#endif /* !defined (_LANGUAGE_ASSEMBLY) */
118 118
119/* 119/*
120 * SDRAM Register Offsets 120 * SDRAM register offsets
121 */ 121 */
122#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100) 122#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
123#define MEM_SDMODE0 (0x0000) 123 defined(CONFIG_SOC_AU1100)
124#define MEM_SDMODE1 (0x0004) 124#define MEM_SDMODE0 0x0000
125#define MEM_SDMODE2 (0x0008) 125#define MEM_SDMODE1 0x0004
126#define MEM_SDADDR0 (0x000C) 126#define MEM_SDMODE2 0x0008
127#define MEM_SDADDR1 (0x0010) 127#define MEM_SDADDR0 0x000C
128#define MEM_SDADDR2 (0x0014) 128#define MEM_SDADDR1 0x0010
129#define MEM_SDREFCFG (0x0018) 129#define MEM_SDADDR2 0x0014
130#define MEM_SDPRECMD (0x001C) 130#define MEM_SDREFCFG 0x0018
131#define MEM_SDAUTOREF (0x0020) 131#define MEM_SDPRECMD 0x001C
132#define MEM_SDWRMD0 (0x0024) 132#define MEM_SDAUTOREF 0x0020
133#define MEM_SDWRMD1 (0x0028) 133#define MEM_SDWRMD0 0x0024
134#define MEM_SDWRMD2 (0x002C) 134#define MEM_SDWRMD1 0x0028
135#define MEM_SDSLEEP (0x0030) 135#define MEM_SDWRMD2 0x002C
136#define MEM_SDSMCKE (0x0034) 136#define MEM_SDSLEEP 0x0030
137#define MEM_SDSMCKE 0x0034
137 138
138/* 139/*
139 * MEM_SDMODE register content definitions 140 * MEM_SDMODE register content definitions
140 */ 141 */
141#define MEM_SDMODE_F (1<<22) 142#define MEM_SDMODE_F (1 << 22)
142#define MEM_SDMODE_SR (1<<21) 143#define MEM_SDMODE_SR (1 << 21)
143#define MEM_SDMODE_BS (1<<20) 144#define MEM_SDMODE_BS (1 << 20)
144#define MEM_SDMODE_RS (3<<18) 145#define MEM_SDMODE_RS (3 << 18)
145#define MEM_SDMODE_CS (7<<15) 146#define MEM_SDMODE_CS (7 << 15)
146#define MEM_SDMODE_TRAS (15<<11) 147#define MEM_SDMODE_TRAS (15 << 11)
147#define MEM_SDMODE_TMRD (3<<9) 148#define MEM_SDMODE_TMRD (3 << 9)
148#define MEM_SDMODE_TWR (3<<7) 149#define MEM_SDMODE_TWR (3 << 7)
149#define MEM_SDMODE_TRP (3<<5) 150#define MEM_SDMODE_TRP (3 << 5)
150#define MEM_SDMODE_TRCD (3<<3) 151#define MEM_SDMODE_TRCD (3 << 3)
151#define MEM_SDMODE_TCL (7<<0) 152#define MEM_SDMODE_TCL (7 << 0)
152 153
153#define MEM_SDMODE_BS_2Bank (0<<20) 154#define MEM_SDMODE_BS_2Bank (0 << 20)
154#define MEM_SDMODE_BS_4Bank (1<<20) 155#define MEM_SDMODE_BS_4Bank (1 << 20)
155#define MEM_SDMODE_RS_11Row (0<<18) 156#define MEM_SDMODE_RS_11Row (0 << 18)
156#define MEM_SDMODE_RS_12Row (1<<18) 157#define MEM_SDMODE_RS_12Row (1 << 18)
157#define MEM_SDMODE_RS_13Row (2<<18) 158#define MEM_SDMODE_RS_13Row (2 << 18)
158#define MEM_SDMODE_RS_N(N) ((N)<<18) 159#define MEM_SDMODE_RS_N(N) ((N) << 18)
159#define MEM_SDMODE_CS_7Col (0<<15) 160#define MEM_SDMODE_CS_7Col (0 << 15)
160#define MEM_SDMODE_CS_8Col (1<<15) 161#define MEM_SDMODE_CS_8Col (1 << 15)
161#define MEM_SDMODE_CS_9Col (2<<15) 162#define MEM_SDMODE_CS_9Col (2 << 15)
162#define MEM_SDMODE_CS_10Col (3<<15) 163#define MEM_SDMODE_CS_10Col (3 << 15)
163#define MEM_SDMODE_CS_11Col (4<<15) 164#define MEM_SDMODE_CS_11Col (4 << 15)
164#define MEM_SDMODE_CS_N(N) ((N)<<15) 165#define MEM_SDMODE_CS_N(N) ((N) << 15)
165#define MEM_SDMODE_TRAS_N(N) ((N)<<11) 166#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
166#define MEM_SDMODE_TMRD_N(N) ((N)<<9) 167#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
167#define MEM_SDMODE_TWR_N(N) ((N)<<7) 168#define MEM_SDMODE_TWR_N(N) ((N) << 7)
168#define MEM_SDMODE_TRP_N(N) ((N)<<5) 169#define MEM_SDMODE_TRP_N(N) ((N) << 5)
169#define MEM_SDMODE_TRCD_N(N) ((N)<<3) 170#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
170#define MEM_SDMODE_TCL_N(N) ((N)<<0) 171#define MEM_SDMODE_TCL_N(N) ((N) << 0)
171 172
172/* 173/*
173 * MEM_SDADDR register contents definitions 174 * MEM_SDADDR register contents definitions
174 */ 175 */
175#define MEM_SDADDR_E (1<<20) 176#define MEM_SDADDR_E (1 << 20)
176#define MEM_SDADDR_CSBA (0x03FF<<10) 177#define MEM_SDADDR_CSBA (0x03FF << 10)
177#define MEM_SDADDR_CSMASK (0x03FF<<0) 178#define MEM_SDADDR_CSMASK (0x03FF << 0)
178#define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12) 179#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
179#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22) 180#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
180 181
181/* 182/*
182 * MEM_SDREFCFG register content definitions 183 * MEM_SDREFCFG register content definitions
183 */ 184 */
184#define MEM_SDREFCFG_TRC (15<<28) 185#define MEM_SDREFCFG_TRC (15 << 28)
185#define MEM_SDREFCFG_TRPM (3<<26) 186#define MEM_SDREFCFG_TRPM (3 << 26)
186#define MEM_SDREFCFG_E (1<<25) 187#define MEM_SDREFCFG_E (1 << 25)
187#define MEM_SDREFCFG_RE (0x1ffffff<<0) 188#define MEM_SDREFCFG_RE (0x1ffffff << 0)
188#define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC) 189#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
189#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM) 190#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
190#define MEM_SDREFCFG_REF_N(N) (N) 191#define MEM_SDREFCFG_REF_N(N) (N)
191#endif 192#endif
192 193
@@ -199,25 +200,25 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
199/***********************************************************************/ 200/***********************************************************************/
200 201
201#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 202#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
202#define MEM_SDMODE0 (0x0800) 203#define MEM_SDMODE0 0x0800
203#define MEM_SDMODE1 (0x0808) 204#define MEM_SDMODE1 0x0808
204#define MEM_SDMODE2 (0x0810) 205#define MEM_SDMODE2 0x0810
205#define MEM_SDADDR0 (0x0820) 206#define MEM_SDADDR0 0x0820
206#define MEM_SDADDR1 (0x0828) 207#define MEM_SDADDR1 0x0828
207#define MEM_SDADDR2 (0x0830) 208#define MEM_SDADDR2 0x0830
208#define MEM_SDCONFIGA (0x0840) 209#define MEM_SDCONFIGA 0x0840
209#define MEM_SDCONFIGB (0x0848) 210#define MEM_SDCONFIGB 0x0848
210#define MEM_SDSTAT (0x0850) 211#define MEM_SDSTAT 0x0850
211#define MEM_SDERRADDR (0x0858) 212#define MEM_SDERRADDR 0x0858
212#define MEM_SDSTRIDE0 (0x0860) 213#define MEM_SDSTRIDE0 0x0860
213#define MEM_SDSTRIDE1 (0x0868) 214#define MEM_SDSTRIDE1 0x0868
214#define MEM_SDSTRIDE2 (0x0870) 215#define MEM_SDSTRIDE2 0x0870
215#define MEM_SDWRMD0 (0x0880) 216#define MEM_SDWRMD0 0x0880
216#define MEM_SDWRMD1 (0x0888) 217#define MEM_SDWRMD1 0x0888
217#define MEM_SDWRMD2 (0x0890) 218#define MEM_SDWRMD2 0x0890
218#define MEM_SDPRECMD (0x08C0) 219#define MEM_SDPRECMD 0x08C0
219#define MEM_SDAUTOREF (0x08C8) 220#define MEM_SDAUTOREF 0x08C8
220#define MEM_SDSREF (0x08D0) 221#define MEM_SDSREF 0x08D0
221#define MEM_SDSLEEP MEM_SDSREF 222#define MEM_SDSLEEP MEM_SDSREF
222 223
223#endif 224#endif
@@ -256,9 +257,9 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
256#define SSI0_PHYS_ADDR 0x11600000 257#define SSI0_PHYS_ADDR 0x11600000
257#define SSI1_PHYS_ADDR 0x11680000 258#define SSI1_PHYS_ADDR 0x11680000
258#define SYS_PHYS_ADDR 0x11900000 259#define SYS_PHYS_ADDR 0x11900000
259#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 260#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
260#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 261#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
261#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 262#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
262#endif 263#endif
263 264
264/********************************************************************/ 265/********************************************************************/
@@ -290,13 +291,13 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
290#define UART3_PHYS_ADDR 0x11400000 291#define UART3_PHYS_ADDR 0x11400000
291#define GPIO2_PHYS_ADDR 0x11700000 292#define GPIO2_PHYS_ADDR 0x11700000
292#define SYS_PHYS_ADDR 0x11900000 293#define SYS_PHYS_ADDR 0x11900000
293#define PCI_MEM_PHYS_ADDR 0x400000000ULL 294#define PCI_MEM_PHYS_ADDR 0x400000000ULL
294#define PCI_IO_PHYS_ADDR 0x500000000ULL 295#define PCI_IO_PHYS_ADDR 0x500000000ULL
295#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL 296#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
296#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL 297#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
297#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 298#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
298#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 299#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
299#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 300#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
300#endif 301#endif
301 302
302/********************************************************************/ 303/********************************************************************/
@@ -333,9 +334,9 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
333#define GPIO2_PHYS_ADDR 0x11700000 334#define GPIO2_PHYS_ADDR 0x11700000
334#define SYS_PHYS_ADDR 0x11900000 335#define SYS_PHYS_ADDR 0x11900000
335#define LCD_PHYS_ADDR 0x15000000 336#define LCD_PHYS_ADDR 0x15000000
336#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 337#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
337#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 338#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
338#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 339#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
339#endif 340#endif
340 341
341/***********************************************************************/ 342/***********************************************************************/
@@ -360,17 +361,17 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
360#define SYS_PHYS_ADDR 0x11900000 361#define SYS_PHYS_ADDR 0x11900000
361#define DDMA_PHYS_ADDR 0x14002000 362#define DDMA_PHYS_ADDR 0x14002000
362#define PE_PHYS_ADDR 0x14008000 363#define PE_PHYS_ADDR 0x14008000
363#define PSC0_PHYS_ADDR 0x11A00000 364#define PSC0_PHYS_ADDR 0x11A00000
364#define PSC1_PHYS_ADDR 0x11B00000 365#define PSC1_PHYS_ADDR 0x11B00000
365#define PSC2_PHYS_ADDR 0x10A00000 366#define PSC2_PHYS_ADDR 0x10A00000
366#define PSC3_PHYS_ADDR 0x10B00000 367#define PSC3_PHYS_ADDR 0x10B00000
367#define PCI_MEM_PHYS_ADDR 0x400000000ULL 368#define PCI_MEM_PHYS_ADDR 0x400000000ULL
368#define PCI_IO_PHYS_ADDR 0x500000000ULL 369#define PCI_IO_PHYS_ADDR 0x500000000ULL
369#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL 370#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
370#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL 371#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
371#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 372#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
372#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 373#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
373#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 374#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
374#endif 375#endif
375 376
376/***********************************************************************/ 377/***********************************************************************/
@@ -397,122 +398,121 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
397#define SWCNT_PHYS_ADDR 0x1110010C 398#define SWCNT_PHYS_ADDR 0x1110010C
398#define MAEFE_PHYS_ADDR 0x14012000 399#define MAEFE_PHYS_ADDR 0x14012000
399#define MAEBE_PHYS_ADDR 0x14010000 400#define MAEBE_PHYS_ADDR 0x14010000
400#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 401#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
401#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 402#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
402#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 403#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
403#endif 404#endif
404 405
405
406/* Static Bus Controller */ 406/* Static Bus Controller */
407#define MEM_STCFG0 0xB4001000 407#define MEM_STCFG0 0xB4001000
408#define MEM_STTIME0 0xB4001004 408#define MEM_STTIME0 0xB4001004
409#define MEM_STADDR0 0xB4001008 409#define MEM_STADDR0 0xB4001008
410 410
411#define MEM_STCFG1 0xB4001010 411#define MEM_STCFG1 0xB4001010
412#define MEM_STTIME1 0xB4001014 412#define MEM_STTIME1 0xB4001014
413#define MEM_STADDR1 0xB4001018 413#define MEM_STADDR1 0xB4001018
414 414
415#define MEM_STCFG2 0xB4001020 415#define MEM_STCFG2 0xB4001020
416#define MEM_STTIME2 0xB4001024 416#define MEM_STTIME2 0xB4001024
417#define MEM_STADDR2 0xB4001028 417#define MEM_STADDR2 0xB4001028
418 418
419#define MEM_STCFG3 0xB4001030 419#define MEM_STCFG3 0xB4001030
420#define MEM_STTIME3 0xB4001034 420#define MEM_STTIME3 0xB4001034
421#define MEM_STADDR3 0xB4001038 421#define MEM_STADDR3 0xB4001038
422 422
423#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 423#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
424#define MEM_STNDCTL 0xB4001100 424#define MEM_STNDCTL 0xB4001100
425#define MEM_STSTAT 0xB4001104 425#define MEM_STSTAT 0xB4001104
426 426
427#define MEM_STNAND_CMD (0x0) 427#define MEM_STNAND_CMD 0x0
428#define MEM_STNAND_ADDR (0x4) 428#define MEM_STNAND_ADDR 0x4
429#define MEM_STNAND_DATA (0x20) 429#define MEM_STNAND_DATA 0x20
430#endif 430#endif
431 431
432/* Interrupt Controller 0 */ 432/* Interrupt Controller 0 */
433#define IC0_CFG0RD 0xB0400040 433#define IC0_CFG0RD 0xB0400040
434#define IC0_CFG0SET 0xB0400040 434#define IC0_CFG0SET 0xB0400040
435#define IC0_CFG0CLR 0xB0400044 435#define IC0_CFG0CLR 0xB0400044
436 436
437#define IC0_CFG1RD 0xB0400048 437#define IC0_CFG1RD 0xB0400048
438#define IC0_CFG1SET 0xB0400048 438#define IC0_CFG1SET 0xB0400048
439#define IC0_CFG1CLR 0xB040004C 439#define IC0_CFG1CLR 0xB040004C
440 440
441#define IC0_CFG2RD 0xB0400050 441#define IC0_CFG2RD 0xB0400050
442#define IC0_CFG2SET 0xB0400050 442#define IC0_CFG2SET 0xB0400050
443#define IC0_CFG2CLR 0xB0400054 443#define IC0_CFG2CLR 0xB0400054
444 444
445#define IC0_REQ0INT 0xB0400054 445#define IC0_REQ0INT 0xB0400054
446#define IC0_SRCRD 0xB0400058 446#define IC0_SRCRD 0xB0400058
447#define IC0_SRCSET 0xB0400058 447#define IC0_SRCSET 0xB0400058
448#define IC0_SRCCLR 0xB040005C 448#define IC0_SRCCLR 0xB040005C
449#define IC0_REQ1INT 0xB040005C 449#define IC0_REQ1INT 0xB040005C
450 450
451#define IC0_ASSIGNRD 0xB0400060 451#define IC0_ASSIGNRD 0xB0400060
452#define IC0_ASSIGNSET 0xB0400060 452#define IC0_ASSIGNSET 0xB0400060
453#define IC0_ASSIGNCLR 0xB0400064 453#define IC0_ASSIGNCLR 0xB0400064
454 454
455#define IC0_WAKERD 0xB0400068 455#define IC0_WAKERD 0xB0400068
456#define IC0_WAKESET 0xB0400068 456#define IC0_WAKESET 0xB0400068
457#define IC0_WAKECLR 0xB040006C 457#define IC0_WAKECLR 0xB040006C
458 458
459#define IC0_MASKRD 0xB0400070 459#define IC0_MASKRD 0xB0400070
460#define IC0_MASKSET 0xB0400070 460#define IC0_MASKSET 0xB0400070
461#define IC0_MASKCLR 0xB0400074 461#define IC0_MASKCLR 0xB0400074
462 462
463#define IC0_RISINGRD 0xB0400078 463#define IC0_RISINGRD 0xB0400078
464#define IC0_RISINGCLR 0xB0400078 464#define IC0_RISINGCLR 0xB0400078
465#define IC0_FALLINGRD 0xB040007C 465#define IC0_FALLINGRD 0xB040007C
466#define IC0_FALLINGCLR 0xB040007C 466#define IC0_FALLINGCLR 0xB040007C
467 467
468#define IC0_TESTBIT 0xB0400080 468#define IC0_TESTBIT 0xB0400080
469 469
470/* Interrupt Controller 1 */ 470/* Interrupt Controller 1 */
471#define IC1_CFG0RD 0xB1800040 471#define IC1_CFG0RD 0xB1800040
472#define IC1_CFG0SET 0xB1800040 472#define IC1_CFG0SET 0xB1800040
473#define IC1_CFG0CLR 0xB1800044 473#define IC1_CFG0CLR 0xB1800044
474 474
475#define IC1_CFG1RD 0xB1800048 475#define IC1_CFG1RD 0xB1800048
476#define IC1_CFG1SET 0xB1800048 476#define IC1_CFG1SET 0xB1800048
477#define IC1_CFG1CLR 0xB180004C 477#define IC1_CFG1CLR 0xB180004C
478 478
479#define IC1_CFG2RD 0xB1800050 479#define IC1_CFG2RD 0xB1800050
480#define IC1_CFG2SET 0xB1800050 480#define IC1_CFG2SET 0xB1800050
481#define IC1_CFG2CLR 0xB1800054 481#define IC1_CFG2CLR 0xB1800054
482 482
483#define IC1_REQ0INT 0xB1800054 483#define IC1_REQ0INT 0xB1800054
484#define IC1_SRCRD 0xB1800058 484#define IC1_SRCRD 0xB1800058
485#define IC1_SRCSET 0xB1800058 485#define IC1_SRCSET 0xB1800058
486#define IC1_SRCCLR 0xB180005C 486#define IC1_SRCCLR 0xB180005C
487#define IC1_REQ1INT 0xB180005C 487#define IC1_REQ1INT 0xB180005C
488 488
489#define IC1_ASSIGNRD 0xB1800060 489#define IC1_ASSIGNRD 0xB1800060
490#define IC1_ASSIGNSET 0xB1800060 490#define IC1_ASSIGNSET 0xB1800060
491#define IC1_ASSIGNCLR 0xB1800064 491#define IC1_ASSIGNCLR 0xB1800064
492 492
493#define IC1_WAKERD 0xB1800068 493#define IC1_WAKERD 0xB1800068
494#define IC1_WAKESET 0xB1800068 494#define IC1_WAKESET 0xB1800068
495#define IC1_WAKECLR 0xB180006C 495#define IC1_WAKECLR 0xB180006C
496 496
497#define IC1_MASKRD 0xB1800070 497#define IC1_MASKRD 0xB1800070
498#define IC1_MASKSET 0xB1800070 498#define IC1_MASKSET 0xB1800070
499#define IC1_MASKCLR 0xB1800074 499#define IC1_MASKCLR 0xB1800074
500 500
501#define IC1_RISINGRD 0xB1800078 501#define IC1_RISINGRD 0xB1800078
502#define IC1_RISINGCLR 0xB1800078 502#define IC1_RISINGCLR 0xB1800078
503#define IC1_FALLINGRD 0xB180007C 503#define IC1_FALLINGRD 0xB180007C
504#define IC1_FALLINGCLR 0xB180007C 504#define IC1_FALLINGCLR 0xB180007C
505 505
506#define IC1_TESTBIT 0xB1800080 506#define IC1_TESTBIT 0xB1800080
507 507
508/* Interrupt Configuration Modes */ 508/* Interrupt Configuration Modes */
509#define INTC_INT_DISABLED 0 509#define INTC_INT_DISABLED 0x0
510#define INTC_INT_RISE_EDGE 0x1 510#define INTC_INT_RISE_EDGE 0x1
511#define INTC_INT_FALL_EDGE 0x2 511#define INTC_INT_FALL_EDGE 0x2
512#define INTC_INT_RISE_AND_FALL_EDGE 0x3 512#define INTC_INT_RISE_AND_FALL_EDGE 0x3
513#define INTC_INT_HIGH_LEVEL 0x5 513#define INTC_INT_HIGH_LEVEL 0x5
514#define INTC_INT_LOW_LEVEL 0x6 514#define INTC_INT_LOW_LEVEL 0x6
515#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 515#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
516 516
517/* Interrupt Numbers */ 517/* Interrupt Numbers */
518/* Au1000 */ 518/* Au1000 */
@@ -579,18 +579,18 @@ enum soc_au1000_ints {
579 AU1000_GPIO_31, 579 AU1000_GPIO_31,
580}; 580};
581 581
582#define UART0_ADDR 0xB1100000 582#define UART0_ADDR 0xB1100000
583#define UART1_ADDR 0xB1200000 583#define UART1_ADDR 0xB1200000
584#define UART2_ADDR 0xB1300000 584#define UART2_ADDR 0xB1300000
585#define UART3_ADDR 0xB1400000 585#define UART3_ADDR 0xB1400000
586 586
587#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap 587#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
588#define USB_HOST_CONFIG 0xB017fffc 588#define USB_HOST_CONFIG 0xB017FFFC
589 589
590#define AU1000_ETH0_BASE 0xB0500000 590#define AU1000_ETH0_BASE 0xB0500000
591#define AU1000_ETH1_BASE 0xB0510000 591#define AU1000_ETH1_BASE 0xB0510000
592#define AU1000_MAC0_ENABLE 0xB0520000 592#define AU1000_MAC0_ENABLE 0xB0520000
593#define AU1000_MAC1_ENABLE 0xB0520004 593#define AU1000_MAC1_ENABLE 0xB0520004
594#define NUM_ETH_INTERFACES 2 594#define NUM_ETH_INTERFACES 2
595#endif /* CONFIG_SOC_AU1000 */ 595#endif /* CONFIG_SOC_AU1000 */
596 596
@@ -662,16 +662,16 @@ enum soc_au1500_ints {
662#define INTC AU1000_PCI_INTC 662#define INTC AU1000_PCI_INTC
663#define INTD AU1000_PCI_INTD 663#define INTD AU1000_PCI_INTD
664 664
665#define UART0_ADDR 0xB1100000 665#define UART0_ADDR 0xB1100000
666#define UART3_ADDR 0xB1400000 666#define UART3_ADDR 0xB1400000
667 667
668#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap 668#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
669#define USB_HOST_CONFIG 0xB017fffc 669#define USB_HOST_CONFIG 0xB017fffc
670 670
671#define AU1500_ETH0_BASE 0xB1500000 671#define AU1500_ETH0_BASE 0xB1500000
672#define AU1500_ETH1_BASE 0xB1510000 672#define AU1500_ETH1_BASE 0xB1510000
673#define AU1500_MAC0_ENABLE 0xB1520000 673#define AU1500_MAC0_ENABLE 0xB1520000
674#define AU1500_MAC1_ENABLE 0xB1520004 674#define AU1500_MAC1_ENABLE 0xB1520004
675#define NUM_ETH_INTERFACES 2 675#define NUM_ETH_INTERFACES 2
676#endif /* CONFIG_SOC_AU1500 */ 676#endif /* CONFIG_SOC_AU1500 */
677 677
@@ -739,15 +739,15 @@ enum soc_au1100_ints {
739 AU1000_GPIO_31, 739 AU1000_GPIO_31,
740}; 740};
741 741
742#define UART0_ADDR 0xB1100000 742#define UART0_ADDR 0xB1100000
743#define UART1_ADDR 0xB1200000 743#define UART1_ADDR 0xB1200000
744#define UART3_ADDR 0xB1400000 744#define UART3_ADDR 0xB1400000
745 745
746#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap 746#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
747#define USB_HOST_CONFIG 0xB017fffc 747#define USB_HOST_CONFIG 0xB017FFFC
748 748
749#define AU1100_ETH0_BASE 0xB0500000 749#define AU1100_ETH0_BASE 0xB0500000
750#define AU1100_MAC0_ENABLE 0xB0520000 750#define AU1100_MAC0_ENABLE 0xB0520000
751#define NUM_ETH_INTERFACES 1 751#define NUM_ETH_INTERFACES 1
752#endif /* CONFIG_SOC_AU1100 */ 752#endif /* CONFIG_SOC_AU1100 */
753 753
@@ -826,18 +826,18 @@ enum soc_au1550_ints {
826#define INTC AU1550_PCI_INTC 826#define INTC AU1550_PCI_INTC
827#define INTD AU1550_PCI_INTD 827#define INTD AU1550_PCI_INTD
828 828
829#define UART0_ADDR 0xB1100000 829#define UART0_ADDR 0xB1100000
830#define UART1_ADDR 0xB1200000 830#define UART1_ADDR 0xB1200000
831#define UART3_ADDR 0xB1400000 831#define UART3_ADDR 0xB1400000
832 832
833#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap 833#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
834#define USB_OHCI_LEN 0x00060000 834#define USB_OHCI_LEN 0x00060000
835#define USB_HOST_CONFIG 0xB4027ffc 835#define USB_HOST_CONFIG 0xB4027ffc
836 836
837#define AU1550_ETH0_BASE 0xB0500000 837#define AU1550_ETH0_BASE 0xB0500000
838#define AU1550_ETH1_BASE 0xB0510000 838#define AU1550_ETH1_BASE 0xB0510000
839#define AU1550_MAC0_ENABLE 0xB0520000 839#define AU1550_MAC0_ENABLE 0xB0520000
840#define AU1550_MAC1_ENABLE 0xB0520004 840#define AU1550_MAC1_ENABLE 0xB0520004
841#define NUM_ETH_INTERFACES 2 841#define NUM_ETH_INTERFACES 2
842#endif /* CONFIG_SOC_AU1550 */ 842#endif /* CONFIG_SOC_AU1550 */
843 843
@@ -911,32 +911,32 @@ enum soc_au1200_ints {
911 AU1000_GPIO_31, 911 AU1000_GPIO_31,
912}; 912};
913 913
914#define UART0_ADDR 0xB1100000 914#define UART0_ADDR 0xB1100000
915#define UART1_ADDR 0xB1200000 915#define UART1_ADDR 0xB1200000
916 916
917#define USB_UOC_BASE 0x14020020 917#define USB_UOC_BASE 0x14020020
918#define USB_UOC_LEN 0x20 918#define USB_UOC_LEN 0x20
919#define USB_OHCI_BASE 0x14020100 919#define USB_OHCI_BASE 0x14020100
920#define USB_OHCI_LEN 0x100 920#define USB_OHCI_LEN 0x100
921#define USB_EHCI_BASE 0x14020200 921#define USB_EHCI_BASE 0x14020200
922#define USB_EHCI_LEN 0x100 922#define USB_EHCI_LEN 0x100
923#define USB_UDC_BASE 0x14022000 923#define USB_UDC_BASE 0x14022000
924#define USB_UDC_LEN 0x2000 924#define USB_UDC_LEN 0x2000
925#define USB_MSR_BASE 0xB4020000 925#define USB_MSR_BASE 0xB4020000
926#define USB_MSR_MCFG 4 926#define USB_MSR_MCFG 4
927#define USBMSRMCFG_OMEMEN 0 927#define USBMSRMCFG_OMEMEN 0
928#define USBMSRMCFG_OBMEN 1 928#define USBMSRMCFG_OBMEN 1
929#define USBMSRMCFG_EMEMEN 2 929#define USBMSRMCFG_EMEMEN 2
930#define USBMSRMCFG_EBMEN 3 930#define USBMSRMCFG_EBMEN 3
931#define USBMSRMCFG_DMEMEN 4 931#define USBMSRMCFG_DMEMEN 4
932#define USBMSRMCFG_DBMEN 5 932#define USBMSRMCFG_DBMEN 5
933#define USBMSRMCFG_GMEMEN 6 933#define USBMSRMCFG_GMEMEN 6
934#define USBMSRMCFG_OHCCLKEN 16 934#define USBMSRMCFG_OHCCLKEN 16
935#define USBMSRMCFG_EHCCLKEN 17 935#define USBMSRMCFG_EHCCLKEN 17
936#define USBMSRMCFG_UDCCLKEN 18 936#define USBMSRMCFG_UDCCLKEN 18
937#define USBMSRMCFG_PHYPLLEN 19 937#define USBMSRMCFG_PHYPLLEN 19
938#define USBMSRMCFG_RDCOMB 30 938#define USBMSRMCFG_RDCOMB 30
939#define USBMSRMCFG_PFEN 31 939#define USBMSRMCFG_PFEN 31
940 940
941#endif /* CONFIG_SOC_AU1200 */ 941#endif /* CONFIG_SOC_AU1200 */
942 942
@@ -949,259 +949,258 @@ enum soc_au1200_ints {
949#define INTX 0xFF /* not valid */ 949#define INTX 0xFF /* not valid */
950 950
951/* Programmable Counters 0 and 1 */ 951/* Programmable Counters 0 and 1 */
952#define SYS_BASE 0xB1900000 952#define SYS_BASE 0xB1900000
953#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 953#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
954# define SYS_CNTRL_E1S (1<<23) 954# define SYS_CNTRL_E1S (1 << 23)
955# define SYS_CNTRL_T1S (1<<20) 955# define SYS_CNTRL_T1S (1 << 20)
956# define SYS_CNTRL_M21 (1<<19) 956# define SYS_CNTRL_M21 (1 << 19)
957# define SYS_CNTRL_M11 (1<<18) 957# define SYS_CNTRL_M11 (1 << 18)
958# define SYS_CNTRL_M01 (1<<17) 958# define SYS_CNTRL_M01 (1 << 17)
959# define SYS_CNTRL_C1S (1<<16) 959# define SYS_CNTRL_C1S (1 << 16)
960# define SYS_CNTRL_BP (1<<14) 960# define SYS_CNTRL_BP (1 << 14)
961# define SYS_CNTRL_EN1 (1<<13) 961# define SYS_CNTRL_EN1 (1 << 13)
962# define SYS_CNTRL_BT1 (1<<12) 962# define SYS_CNTRL_BT1 (1 << 12)
963# define SYS_CNTRL_EN0 (1<<11) 963# define SYS_CNTRL_EN0 (1 << 11)
964# define SYS_CNTRL_BT0 (1<<10) 964# define SYS_CNTRL_BT0 (1 << 10)
965# define SYS_CNTRL_E0 (1<<8) 965# define SYS_CNTRL_E0 (1 << 8)
966# define SYS_CNTRL_E0S (1<<7) 966# define SYS_CNTRL_E0S (1 << 7)
967# define SYS_CNTRL_32S (1<<5) 967# define SYS_CNTRL_32S (1 << 5)
968# define SYS_CNTRL_T0S (1<<4) 968# define SYS_CNTRL_T0S (1 << 4)
969# define SYS_CNTRL_M20 (1<<3) 969# define SYS_CNTRL_M20 (1 << 3)
970# define SYS_CNTRL_M10 (1<<2) 970# define SYS_CNTRL_M10 (1 << 2)
971# define SYS_CNTRL_M00 (1<<1) 971# define SYS_CNTRL_M00 (1 << 1)
972# define SYS_CNTRL_C0S (1<<0) 972# define SYS_CNTRL_C0S (1 << 0)
973 973
974/* Programmable Counter 0 Registers */ 974/* Programmable Counter 0 Registers */
975#define SYS_TOYTRIM (SYS_BASE + 0) 975#define SYS_TOYTRIM (SYS_BASE + 0)
976#define SYS_TOYWRITE (SYS_BASE + 4) 976#define SYS_TOYWRITE (SYS_BASE + 4)
977#define SYS_TOYMATCH0 (SYS_BASE + 8) 977#define SYS_TOYMATCH0 (SYS_BASE + 8)
978#define SYS_TOYMATCH1 (SYS_BASE + 0xC) 978#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
979#define SYS_TOYMATCH2 (SYS_BASE + 0x10) 979#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
980#define SYS_TOYREAD (SYS_BASE + 0x40) 980#define SYS_TOYREAD (SYS_BASE + 0x40)
981 981
982/* Programmable Counter 1 Registers */ 982/* Programmable Counter 1 Registers */
983#define SYS_RTCTRIM (SYS_BASE + 0x44) 983#define SYS_RTCTRIM (SYS_BASE + 0x44)
984#define SYS_RTCWRITE (SYS_BASE + 0x48) 984#define SYS_RTCWRITE (SYS_BASE + 0x48)
985#define SYS_RTCMATCH0 (SYS_BASE + 0x4C) 985#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
986#define SYS_RTCMATCH1 (SYS_BASE + 0x50) 986#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
987#define SYS_RTCMATCH2 (SYS_BASE + 0x54) 987#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
988#define SYS_RTCREAD (SYS_BASE + 0x58) 988#define SYS_RTCREAD (SYS_BASE + 0x58)
989 989
990/* I2S Controller */ 990/* I2S Controller */
991#define I2S_DATA 0xB1000000 991#define I2S_DATA 0xB1000000
992# define I2S_DATA_MASK (0xffffff) 992# define I2S_DATA_MASK 0xffffff
993#define I2S_CONFIG 0xB1000004 993#define I2S_CONFIG 0xB1000004
994# define I2S_CONFIG_XU (1<<25) 994# define I2S_CONFIG_XU (1 << 25)
995# define I2S_CONFIG_XO (1<<24) 995# define I2S_CONFIG_XO (1 << 24)
996# define I2S_CONFIG_RU (1<<23) 996# define I2S_CONFIG_RU (1 << 23)
997# define I2S_CONFIG_RO (1<<22) 997# define I2S_CONFIG_RO (1 << 22)
998# define I2S_CONFIG_TR (1<<21) 998# define I2S_CONFIG_TR (1 << 21)
999# define I2S_CONFIG_TE (1<<20) 999# define I2S_CONFIG_TE (1 << 20)
1000# define I2S_CONFIG_TF (1<<19) 1000# define I2S_CONFIG_TF (1 << 19)
1001# define I2S_CONFIG_RR (1<<18) 1001# define I2S_CONFIG_RR (1 << 18)
1002# define I2S_CONFIG_RE (1<<17) 1002# define I2S_CONFIG_RE (1 << 17)
1003# define I2S_CONFIG_RF (1<<16) 1003# define I2S_CONFIG_RF (1 << 16)
1004# define I2S_CONFIG_PD (1<<11) 1004# define I2S_CONFIG_PD (1 << 11)
1005# define I2S_CONFIG_LB (1<<10) 1005# define I2S_CONFIG_LB (1 << 10)
1006# define I2S_CONFIG_IC (1<<9) 1006# define I2S_CONFIG_IC (1 << 9)
1007# define I2S_CONFIG_FM_BIT 7 1007# define I2S_CONFIG_FM_BIT 7
1008# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) 1008# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1009# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) 1009# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1010# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) 1010# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1011# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) 1011# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1012# define I2S_CONFIG_TN (1<<6) 1012# define I2S_CONFIG_TN (1 << 6)
1013# define I2S_CONFIG_RN (1<<5) 1013# define I2S_CONFIG_RN (1 << 5)
1014# define I2S_CONFIG_SZ_BIT 0 1014# define I2S_CONFIG_SZ_BIT 0
1015# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) 1015# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1016 1016
1017#define I2S_CONTROL 0xB1000008 1017#define I2S_CONTROL 0xB1000008
1018# define I2S_CONTROL_D (1<<1) 1018# define I2S_CONTROL_D (1 << 1)
1019# define I2S_CONTROL_CE (1<<0) 1019# define I2S_CONTROL_CE (1 << 0)
1020 1020
1021/* USB Host Controller */ 1021/* USB Host Controller */
1022#ifndef USB_OHCI_LEN 1022#ifndef USB_OHCI_LEN
1023#define USB_OHCI_LEN 0x00100000 1023#define USB_OHCI_LEN 0x00100000
1024#endif 1024#endif
1025 1025
1026#ifndef CONFIG_SOC_AU1200 1026#ifndef CONFIG_SOC_AU1200
1027 1027
1028/* USB Device Controller */ 1028/* USB Device Controller */
1029#define USBD_EP0RD 0xB0200000 1029#define USBD_EP0RD 0xB0200000
1030#define USBD_EP0WR 0xB0200004 1030#define USBD_EP0WR 0xB0200004
1031#define USBD_EP2WR 0xB0200008 1031#define USBD_EP2WR 0xB0200008
1032#define USBD_EP3WR 0xB020000C 1032#define USBD_EP3WR 0xB020000C
1033#define USBD_EP4RD 0xB0200010 1033#define USBD_EP4RD 0xB0200010
1034#define USBD_EP5RD 0xB0200014 1034#define USBD_EP5RD 0xB0200014
1035#define USBD_INTEN 0xB0200018 1035#define USBD_INTEN 0xB0200018
1036#define USBD_INTSTAT 0xB020001C 1036#define USBD_INTSTAT 0xB020001C
1037# define USBDEV_INT_SOF (1<<12) 1037# define USBDEV_INT_SOF (1 << 12)
1038# define USBDEV_INT_HF_BIT 6 1038# define USBDEV_INT_HF_BIT 6
1039# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) 1039# define USBDEV_INT_HF_MASK 0x3f << USBDEV_INT_HF_BIT)
1040# define USBDEV_INT_CMPLT_BIT 0 1040# define USBDEV_INT_CMPLT_BIT 0
1041# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) 1041# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1042#define USBD_CONFIG 0xB0200020 1042#define USBD_CONFIG 0xB0200020
1043#define USBD_EP0CS 0xB0200024 1043#define USBD_EP0CS 0xB0200024
1044#define USBD_EP2CS 0xB0200028 1044#define USBD_EP2CS 0xB0200028
1045#define USBD_EP3CS 0xB020002C 1045#define USBD_EP3CS 0xB020002C
1046#define USBD_EP4CS 0xB0200030 1046#define USBD_EP4CS 0xB0200030
1047#define USBD_EP5CS 0xB0200034 1047#define USBD_EP5CS 0xB0200034
1048# define USBDEV_CS_SU (1<<14) 1048# define USBDEV_CS_SU (1 << 14)
1049# define USBDEV_CS_NAK (1<<13) 1049# define USBDEV_CS_NAK (1 << 13)
1050# define USBDEV_CS_ACK (1<<12) 1050# define USBDEV_CS_ACK (1 << 12)
1051# define USBDEV_CS_BUSY (1<<11) 1051# define USBDEV_CS_BUSY (1 << 11)
1052# define USBDEV_CS_TSIZE_BIT 1 1052# define USBDEV_CS_TSIZE_BIT 1
1053# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) 1053# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1054# define USBDEV_CS_STALL (1<<0) 1054# define USBDEV_CS_STALL (1 << 0)
1055#define USBD_EP0RDSTAT 0xB0200040 1055#define USBD_EP0RDSTAT 0xB0200040
1056#define USBD_EP0WRSTAT 0xB0200044 1056#define USBD_EP0WRSTAT 0xB0200044
1057#define USBD_EP2WRSTAT 0xB0200048 1057#define USBD_EP2WRSTAT 0xB0200048
1058#define USBD_EP3WRSTAT 0xB020004C 1058#define USBD_EP3WRSTAT 0xB020004C
1059#define USBD_EP4RDSTAT 0xB0200050 1059#define USBD_EP4RDSTAT 0xB0200050
1060#define USBD_EP5RDSTAT 0xB0200054 1060#define USBD_EP5RDSTAT 0xB0200054
1061# define USBDEV_FSTAT_FLUSH (1<<6) 1061# define USBDEV_FSTAT_FLUSH (1 << 6)
1062# define USBDEV_FSTAT_UF (1<<5) 1062# define USBDEV_FSTAT_UF (1 << 5)
1063# define USBDEV_FSTAT_OF (1<<4) 1063# define USBDEV_FSTAT_OF (1 << 4)
1064# define USBDEV_FSTAT_FCNT_BIT 0 1064# define USBDEV_FSTAT_FCNT_BIT 0
1065# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) 1065# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1066#define USBD_ENABLE 0xB0200058 1066#define USBD_ENABLE 0xB0200058
1067# define USBDEV_ENABLE (1<<1) 1067# define USBDEV_ENABLE (1 << 1)
1068# define USBDEV_CE (1<<0) 1068# define USBDEV_CE (1 << 0)
1069 1069
1070#endif /* !CONFIG_SOC_AU1200 */ 1070#endif /* !CONFIG_SOC_AU1200 */
1071 1071
1072/* Ethernet Controllers */ 1072/* Ethernet Controllers */
1073 1073
1074/* 4 byte offsets from AU1000_ETH_BASE */ 1074/* 4 byte offsets from AU1000_ETH_BASE */
1075#define MAC_CONTROL 0x0 1075#define MAC_CONTROL 0x0
1076# define MAC_RX_ENABLE (1<<2) 1076# define MAC_RX_ENABLE (1 << 2)
1077# define MAC_TX_ENABLE (1<<3) 1077# define MAC_TX_ENABLE (1 << 3)
1078# define MAC_DEF_CHECK (1<<5) 1078# define MAC_DEF_CHECK (1 << 5)
1079# define MAC_SET_BL(X) (((X)&0x3)<<6) 1079# define MAC_SET_BL(X) (((X) & 0x3) << 6)
1080# define MAC_AUTO_PAD (1<<8) 1080# define MAC_AUTO_PAD (1 << 8)
1081# define MAC_DISABLE_RETRY (1<<10) 1081# define MAC_DISABLE_RETRY (1 << 10)
1082# define MAC_DISABLE_BCAST (1<<11) 1082# define MAC_DISABLE_BCAST (1 << 11)
1083# define MAC_LATE_COL (1<<12) 1083# define MAC_LATE_COL (1 << 12)
1084# define MAC_HASH_MODE (1<<13) 1084# define MAC_HASH_MODE (1 << 13)
1085# define MAC_HASH_ONLY (1<<15) 1085# define MAC_HASH_ONLY (1 << 15)
1086# define MAC_PASS_ALL (1<<16) 1086# define MAC_PASS_ALL (1 << 16)
1087# define MAC_INVERSE_FILTER (1<<17) 1087# define MAC_INVERSE_FILTER (1 << 17)
1088# define MAC_PROMISCUOUS (1<<18) 1088# define MAC_PROMISCUOUS (1 << 18)
1089# define MAC_PASS_ALL_MULTI (1<<19) 1089# define MAC_PASS_ALL_MULTI (1 << 19)
1090# define MAC_FULL_DUPLEX (1<<20) 1090# define MAC_FULL_DUPLEX (1 << 20)
1091# define MAC_NORMAL_MODE 0 1091# define MAC_NORMAL_MODE 0
1092# define MAC_INT_LOOPBACK (1<<21) 1092# define MAC_INT_LOOPBACK (1 << 21)
1093# define MAC_EXT_LOOPBACK (1<<22) 1093# define MAC_EXT_LOOPBACK (1 << 22)
1094# define MAC_DISABLE_RX_OWN (1<<23) 1094# define MAC_DISABLE_RX_OWN (1 << 23)
1095# define MAC_BIG_ENDIAN (1<<30) 1095# define MAC_BIG_ENDIAN (1 << 30)
1096# define MAC_RX_ALL (1<<31) 1096# define MAC_RX_ALL (1 << 31)
1097#define MAC_ADDRESS_HIGH 0x4 1097#define MAC_ADDRESS_HIGH 0x4
1098#define MAC_ADDRESS_LOW 0x8 1098#define MAC_ADDRESS_LOW 0x8
1099#define MAC_MCAST_HIGH 0xC 1099#define MAC_MCAST_HIGH 0xC
1100#define MAC_MCAST_LOW 0x10 1100#define MAC_MCAST_LOW 0x10
1101#define MAC_MII_CNTRL 0x14 1101#define MAC_MII_CNTRL 0x14
1102# define MAC_MII_BUSY (1<<0) 1102# define MAC_MII_BUSY (1 << 0)
1103# define MAC_MII_READ 0 1103# define MAC_MII_READ 0
1104# define MAC_MII_WRITE (1<<1) 1104# define MAC_MII_WRITE (1 << 1)
1105# define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) 1105# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1106# define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) 1106# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1107#define MAC_MII_DATA 0x18 1107#define MAC_MII_DATA 0x18
1108#define MAC_FLOW_CNTRL 0x1C 1108#define MAC_FLOW_CNTRL 0x1C
1109# define MAC_FLOW_CNTRL_BUSY (1<<0) 1109# define MAC_FLOW_CNTRL_BUSY (1 << 0)
1110# define MAC_FLOW_CNTRL_ENABLE (1<<1) 1110# define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1111# define MAC_PASS_CONTROL (1<<2) 1111# define MAC_PASS_CONTROL (1 << 2)
1112# define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) 1112# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1113#define MAC_VLAN1_TAG 0x20 1113#define MAC_VLAN1_TAG 0x20
1114#define MAC_VLAN2_TAG 0x24 1114#define MAC_VLAN2_TAG 0x24
1115 1115
1116/* Ethernet Controller Enable */ 1116/* Ethernet Controller Enable */
1117 1117
1118# define MAC_EN_CLOCK_ENABLE (1<<0) 1118# define MAC_EN_CLOCK_ENABLE (1 << 0)
1119# define MAC_EN_RESET0 (1<<1) 1119# define MAC_EN_RESET0 (1 << 1)
1120# define MAC_EN_TOSS (0<<2) 1120# define MAC_EN_TOSS (0 << 2)
1121# define MAC_EN_CACHEABLE (1<<3) 1121# define MAC_EN_CACHEABLE (1 << 3)
1122# define MAC_EN_RESET1 (1<<4) 1122# define MAC_EN_RESET1 (1 << 4)
1123# define MAC_EN_RESET2 (1<<5) 1123# define MAC_EN_RESET2 (1 << 5)
1124# define MAC_DMA_RESET (1<<6) 1124# define MAC_DMA_RESET (1 << 6)
1125 1125
1126/* Ethernet Controller DMA Channels */ 1126/* Ethernet Controller DMA Channels */
1127 1127
1128#define MAC0_TX_DMA_ADDR 0xB4004000 1128#define MAC0_TX_DMA_ADDR 0xB4004000
1129#define MAC1_TX_DMA_ADDR 0xB4004200 1129#define MAC1_TX_DMA_ADDR 0xB4004200
1130/* offsets from MAC_TX_RING_ADDR address */ 1130/* offsets from MAC_TX_RING_ADDR address */
1131#define MAC_TX_BUFF0_STATUS 0x0 1131#define MAC_TX_BUFF0_STATUS 0x0
1132# define TX_FRAME_ABORTED (1<<0) 1132# define TX_FRAME_ABORTED (1 << 0)
1133# define TX_JAB_TIMEOUT (1<<1) 1133# define TX_JAB_TIMEOUT (1 << 1)
1134# define TX_NO_CARRIER (1<<2) 1134# define TX_NO_CARRIER (1 << 2)
1135# define TX_LOSS_CARRIER (1<<3) 1135# define TX_LOSS_CARRIER (1 << 3)
1136# define TX_EXC_DEF (1<<4) 1136# define TX_EXC_DEF (1 << 4)
1137# define TX_LATE_COLL_ABORT (1<<5) 1137# define TX_LATE_COLL_ABORT (1 << 5)
1138# define TX_EXC_COLL (1<<6) 1138# define TX_EXC_COLL (1 << 6)
1139# define TX_UNDERRUN (1<<7) 1139# define TX_UNDERRUN (1 << 7)
1140# define TX_DEFERRED (1<<8) 1140# define TX_DEFERRED (1 << 8)
1141# define TX_LATE_COLL (1<<9) 1141# define TX_LATE_COLL (1 << 9)
1142# define TX_COLL_CNT_MASK (0xF<<10) 1142# define TX_COLL_CNT_MASK (0xF << 10)
1143# define TX_PKT_RETRY (1<<31) 1143# define TX_PKT_RETRY (1 << 31)
1144#define MAC_TX_BUFF0_ADDR 0x4 1144#define MAC_TX_BUFF0_ADDR 0x4
1145# define TX_DMA_ENABLE (1<<0) 1145# define TX_DMA_ENABLE (1 << 0)
1146# define TX_T_DONE (1<<1) 1146# define TX_T_DONE (1 << 1)
1147# define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 1147# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1148#define MAC_TX_BUFF0_LEN 0x8 1148#define MAC_TX_BUFF0_LEN 0x8
1149#define MAC_TX_BUFF1_STATUS 0x10 1149#define MAC_TX_BUFF1_STATUS 0x10
1150#define MAC_TX_BUFF1_ADDR 0x14 1150#define MAC_TX_BUFF1_ADDR 0x14
1151#define MAC_TX_BUFF1_LEN 0x18 1151#define MAC_TX_BUFF1_LEN 0x18
1152#define MAC_TX_BUFF2_STATUS 0x20 1152#define MAC_TX_BUFF2_STATUS 0x20
1153#define MAC_TX_BUFF2_ADDR 0x24 1153#define MAC_TX_BUFF2_ADDR 0x24
1154#define MAC_TX_BUFF2_LEN 0x28 1154#define MAC_TX_BUFF2_LEN 0x28
1155#define MAC_TX_BUFF3_STATUS 0x30 1155#define MAC_TX_BUFF3_STATUS 0x30
1156#define MAC_TX_BUFF3_ADDR 0x34 1156#define MAC_TX_BUFF3_ADDR 0x34
1157#define MAC_TX_BUFF3_LEN 0x38 1157#define MAC_TX_BUFF3_LEN 0x38
1158 1158
1159#define MAC0_RX_DMA_ADDR 0xB4004100 1159#define MAC0_RX_DMA_ADDR 0xB4004100
1160#define MAC1_RX_DMA_ADDR 0xB4004300 1160#define MAC1_RX_DMA_ADDR 0xB4004300
1161/* offsets from MAC_RX_RING_ADDR */ 1161/* offsets from MAC_RX_RING_ADDR */
1162#define MAC_RX_BUFF0_STATUS 0x0 1162#define MAC_RX_BUFF0_STATUS 0x0
1163# define RX_FRAME_LEN_MASK 0x3fff 1163# define RX_FRAME_LEN_MASK 0x3fff
1164# define RX_WDOG_TIMER (1<<14) 1164# define RX_WDOG_TIMER (1 << 14)
1165# define RX_RUNT (1<<15) 1165# define RX_RUNT (1 << 15)
1166# define RX_OVERLEN (1<<16) 1166# define RX_OVERLEN (1 << 16)
1167# define RX_COLL (1<<17) 1167# define RX_COLL (1 << 17)
1168# define RX_ETHER (1<<18) 1168# define RX_ETHER (1 << 18)
1169# define RX_MII_ERROR (1<<19) 1169# define RX_MII_ERROR (1 << 19)
1170# define RX_DRIBBLING (1<<20) 1170# define RX_DRIBBLING (1 << 20)
1171# define RX_CRC_ERROR (1<<21) 1171# define RX_CRC_ERROR (1 << 21)
1172# define RX_VLAN1 (1<<22) 1172# define RX_VLAN1 (1 << 22)
1173# define RX_VLAN2 (1<<23) 1173# define RX_VLAN2 (1 << 23)
1174# define RX_LEN_ERROR (1<<24) 1174# define RX_LEN_ERROR (1 << 24)
1175# define RX_CNTRL_FRAME (1<<25) 1175# define RX_CNTRL_FRAME (1 << 25)
1176# define RX_U_CNTRL_FRAME (1<<26) 1176# define RX_U_CNTRL_FRAME (1 << 26)
1177# define RX_MCAST_FRAME (1<<27) 1177# define RX_MCAST_FRAME (1 << 27)
1178# define RX_BCAST_FRAME (1<<28) 1178# define RX_BCAST_FRAME (1 << 28)
1179# define RX_FILTER_FAIL (1<<29) 1179# define RX_FILTER_FAIL (1 << 29)
1180# define RX_PACKET_FILTER (1<<30) 1180# define RX_PACKET_FILTER (1 << 30)
1181# define RX_MISSED_FRAME (1<<31) 1181# define RX_MISSED_FRAME (1 << 31)
1182 1182
1183# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ 1183# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1184 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ 1184 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1185 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 1185 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1186#define MAC_RX_BUFF0_ADDR 0x4 1186#define MAC_RX_BUFF0_ADDR 0x4
1187# define RX_DMA_ENABLE (1<<0) 1187# define RX_DMA_ENABLE (1 << 0)
1188# define RX_T_DONE (1<<1) 1188# define RX_T_DONE (1 << 1)
1189# define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 1189# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1190# define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) 1190# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1191#define MAC_RX_BUFF1_STATUS 0x10 1191#define MAC_RX_BUFF1_STATUS 0x10
1192#define MAC_RX_BUFF1_ADDR 0x14 1192#define MAC_RX_BUFF1_ADDR 0x14
1193#define MAC_RX_BUFF2_STATUS 0x20 1193#define MAC_RX_BUFF2_STATUS 0x20
1194#define MAC_RX_BUFF2_ADDR 0x24 1194#define MAC_RX_BUFF2_ADDR 0x24
1195#define MAC_RX_BUFF3_STATUS 0x30 1195#define MAC_RX_BUFF3_STATUS 0x30
1196#define MAC_RX_BUFF3_ADDR 0x34 1196#define MAC_RX_BUFF3_ADDR 0x34
1197
1198 1197
1199/* UARTS 0-3 */ 1198/* UARTS 0-3 */
1200#define UART_BASE UART0_ADDR 1199#define UART_BASE UART0_ADDR
1201#ifdef CONFIG_SOC_AU1200 1200#ifdef CONFIG_SOC_AU1200
1202#define UART_DEBUG_BASE UART1_ADDR 1201#define UART_DEBUG_BASE UART1_ADDR
1203#else 1202#else
1204#define UART_DEBUG_BASE UART3_ADDR 1203#define UART_DEBUG_BASE UART3_ADDR
1205#endif 1204#endif
1206 1205
1207#define UART_RX 0 /* Receive buffer */ 1206#define UART_RX 0 /* Receive buffer */
@@ -1294,341 +1293,337 @@ enum soc_au1200_ints {
1294#define UART_MSR_DCTS 0x01 /* Delta CTS */ 1293#define UART_MSR_DCTS 0x01 /* Delta CTS */
1295#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ 1294#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1296 1295
1297
1298
1299/* SSIO */ 1296/* SSIO */
1300#define SSI0_STATUS 0xB1600000 1297#define SSI0_STATUS 0xB1600000
1301# define SSI_STATUS_BF (1<<4) 1298# define SSI_STATUS_BF (1 << 4)
1302# define SSI_STATUS_OF (1<<3) 1299# define SSI_STATUS_OF (1 << 3)
1303# define SSI_STATUS_UF (1<<2) 1300# define SSI_STATUS_UF (1 << 2)
1304# define SSI_STATUS_D (1<<1) 1301# define SSI_STATUS_D (1 << 1)
1305# define SSI_STATUS_B (1<<0) 1302# define SSI_STATUS_B (1 << 0)
1306#define SSI0_INT 0xB1600004 1303#define SSI0_INT 0xB1600004
1307# define SSI_INT_OI (1<<3) 1304# define SSI_INT_OI (1 << 3)
1308# define SSI_INT_UI (1<<2) 1305# define SSI_INT_UI (1 << 2)
1309# define SSI_INT_DI (1<<1) 1306# define SSI_INT_DI (1 << 1)
1310#define SSI0_INT_ENABLE 0xB1600008 1307#define SSI0_INT_ENABLE 0xB1600008
1311# define SSI_INTE_OIE (1<<3) 1308# define SSI_INTE_OIE (1 << 3)
1312# define SSI_INTE_UIE (1<<2) 1309# define SSI_INTE_UIE (1 << 2)
1313# define SSI_INTE_DIE (1<<1) 1310# define SSI_INTE_DIE (1 << 1)
1314#define SSI0_CONFIG 0xB1600020 1311#define SSI0_CONFIG 0xB1600020
1315# define SSI_CONFIG_AO (1<<24) 1312# define SSI_CONFIG_AO (1 << 24)
1316# define SSI_CONFIG_DO (1<<23) 1313# define SSI_CONFIG_DO (1 << 23)
1317# define SSI_CONFIG_ALEN_BIT 20 1314# define SSI_CONFIG_ALEN_BIT 20
1318# define SSI_CONFIG_ALEN_MASK (0x7<<20) 1315# define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1319# define SSI_CONFIG_DLEN_BIT 16 1316# define SSI_CONFIG_DLEN_BIT 16
1320# define SSI_CONFIG_DLEN_MASK (0x7<<16) 1317# define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1321# define SSI_CONFIG_DD (1<<11) 1318# define SSI_CONFIG_DD (1 << 11)
1322# define SSI_CONFIG_AD (1<<10) 1319# define SSI_CONFIG_AD (1 << 10)
1323# define SSI_CONFIG_BM_BIT 8 1320# define SSI_CONFIG_BM_BIT 8
1324# define SSI_CONFIG_BM_MASK (0x3<<8) 1321# define SSI_CONFIG_BM_MASK (0x3 << 8)
1325# define SSI_CONFIG_CE (1<<7) 1322# define SSI_CONFIG_CE (1 << 7)
1326# define SSI_CONFIG_DP (1<<6) 1323# define SSI_CONFIG_DP (1 << 6)
1327# define SSI_CONFIG_DL (1<<5) 1324# define SSI_CONFIG_DL (1 << 5)
1328# define SSI_CONFIG_EP (1<<4) 1325# define SSI_CONFIG_EP (1 << 4)
1329#define SSI0_ADATA 0xB1600024 1326#define SSI0_ADATA 0xB1600024
1330# define SSI_AD_D (1<<24) 1327# define SSI_AD_D (1 << 24)
1331# define SSI_AD_ADDR_BIT 16 1328# define SSI_AD_ADDR_BIT 16
1332# define SSI_AD_ADDR_MASK (0xff<<16) 1329# define SSI_AD_ADDR_MASK (0xff << 16)
1333# define SSI_AD_DATA_BIT 0 1330# define SSI_AD_DATA_BIT 0
1334# define SSI_AD_DATA_MASK (0xfff<<0) 1331# define SSI_AD_DATA_MASK (0xfff << 0)
1335#define SSI0_CLKDIV 0xB1600028 1332#define SSI0_CLKDIV 0xB1600028
1336#define SSI0_CONTROL 0xB1600100 1333#define SSI0_CONTROL 0xB1600100
1337# define SSI_CONTROL_CD (1<<1) 1334# define SSI_CONTROL_CD (1 << 1)
1338# define SSI_CONTROL_E (1<<0) 1335# define SSI_CONTROL_E (1 << 0)
1339 1336
1340/* SSI1 */ 1337/* SSI1 */
1341#define SSI1_STATUS 0xB1680000 1338#define SSI1_STATUS 0xB1680000
1342#define SSI1_INT 0xB1680004 1339#define SSI1_INT 0xB1680004
1343#define SSI1_INT_ENABLE 0xB1680008 1340#define SSI1_INT_ENABLE 0xB1680008
1344#define SSI1_CONFIG 0xB1680020 1341#define SSI1_CONFIG 0xB1680020
1345#define SSI1_ADATA 0xB1680024 1342#define SSI1_ADATA 0xB1680024
1346#define SSI1_CLKDIV 0xB1680028 1343#define SSI1_CLKDIV 0xB1680028
1347#define SSI1_ENABLE 0xB1680100 1344#define SSI1_ENABLE 0xB1680100
1348 1345
1349/* 1346/*
1350 * Register content definitions 1347 * Register content definitions
1351 */ 1348 */
1352#define SSI_STATUS_BF (1<<4) 1349#define SSI_STATUS_BF (1 << 4)
1353#define SSI_STATUS_OF (1<<3) 1350#define SSI_STATUS_OF (1 << 3)
1354#define SSI_STATUS_UF (1<<2) 1351#define SSI_STATUS_UF (1 << 2)
1355#define SSI_STATUS_D (1<<1) 1352#define SSI_STATUS_D (1 << 1)
1356#define SSI_STATUS_B (1<<0) 1353#define SSI_STATUS_B (1 << 0)
1357 1354
1358/* SSI_INT */ 1355/* SSI_INT */
1359#define SSI_INT_OI (1<<3) 1356#define SSI_INT_OI (1 << 3)
1360#define SSI_INT_UI (1<<2) 1357#define SSI_INT_UI (1 << 2)
1361#define SSI_INT_DI (1<<1) 1358#define SSI_INT_DI (1 << 1)
1362 1359
1363/* SSI_INTEN */ 1360/* SSI_INTEN */
1364#define SSI_INTEN_OIE (1<<3) 1361#define SSI_INTEN_OIE (1 << 3)
1365#define SSI_INTEN_UIE (1<<2) 1362#define SSI_INTEN_UIE (1 << 2)
1366#define SSI_INTEN_DIE (1<<1) 1363#define SSI_INTEN_DIE (1 << 1)
1367 1364
1368#define SSI_CONFIG_AO (1<<24) 1365#define SSI_CONFIG_AO (1 << 24)
1369#define SSI_CONFIG_DO (1<<23) 1366#define SSI_CONFIG_DO (1 << 23)
1370#define SSI_CONFIG_ALEN (7<<20) 1367#define SSI_CONFIG_ALEN (7 << 20)
1371#define SSI_CONFIG_DLEN (15<<16) 1368#define SSI_CONFIG_DLEN (15 << 16)
1372#define SSI_CONFIG_DD (1<<11) 1369#define SSI_CONFIG_DD (1 << 11)
1373#define SSI_CONFIG_AD (1<<10) 1370#define SSI_CONFIG_AD (1 << 10)
1374#define SSI_CONFIG_BM (3<<8) 1371#define SSI_CONFIG_BM (3 << 8)
1375#define SSI_CONFIG_CE (1<<7) 1372#define SSI_CONFIG_CE (1 << 7)
1376#define SSI_CONFIG_DP (1<<6) 1373#define SSI_CONFIG_DP (1 << 6)
1377#define SSI_CONFIG_DL (1<<5) 1374#define SSI_CONFIG_DL (1 << 5)
1378#define SSI_CONFIG_EP (1<<4) 1375#define SSI_CONFIG_EP (1 << 4)
1379#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20) 1376#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1380#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16) 1377#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1381#define SSI_CONFIG_BM_HI (0<<8) 1378#define SSI_CONFIG_BM_HI (0 << 8)
1382#define SSI_CONFIG_BM_LO (1<<8) 1379#define SSI_CONFIG_BM_LO (1 << 8)
1383#define SSI_CONFIG_BM_CY (2<<8) 1380#define SSI_CONFIG_BM_CY (2 << 8)
1384 1381
1385#define SSI_ADATA_D (1<<24) 1382#define SSI_ADATA_D (1 << 24)
1386#define SSI_ADATA_ADDR (0xFF<<16) 1383#define SSI_ADATA_ADDR (0xFF << 16)
1387#define SSI_ADATA_DATA (0x0FFF) 1384#define SSI_ADATA_DATA 0x0FFF
1388#define SSI_ADATA_ADDR_N(N) (N<<16) 1385#define SSI_ADATA_ADDR_N(N) (N << 16)
1389 1386
1390#define SSI_ENABLE_CD (1<<1) 1387#define SSI_ENABLE_CD (1 << 1)
1391#define SSI_ENABLE_E (1<<0) 1388#define SSI_ENABLE_E (1 << 0)
1392
1393 1389
1394/* IrDA Controller */ 1390/* IrDA Controller */
1395#define IRDA_BASE 0xB0300000 1391#define IRDA_BASE 0xB0300000
1396#define IR_RING_PTR_STATUS (IRDA_BASE+0x00) 1392#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
1397#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) 1393#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
1398#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) 1394#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
1399#define IR_RING_SIZE (IRDA_BASE+0x0C) 1395#define IR_RING_SIZE (IRDA_BASE + 0x0C)
1400#define IR_RING_PROMPT (IRDA_BASE+0x10) 1396#define IR_RING_PROMPT (IRDA_BASE + 0x10)
1401#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) 1397#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
1402#define IR_INT_CLEAR (IRDA_BASE+0x18) 1398#define IR_INT_CLEAR (IRDA_BASE + 0x18)
1403#define IR_CONFIG_1 (IRDA_BASE+0x20) 1399#define IR_CONFIG_1 (IRDA_BASE + 0x20)
1404# define IR_RX_INVERT_LED (1<<0) 1400# define IR_RX_INVERT_LED (1 << 0)
1405# define IR_TX_INVERT_LED (1<<1) 1401# define IR_TX_INVERT_LED (1 << 1)
1406# define IR_ST (1<<2) 1402# define IR_ST (1 << 2)
1407# define IR_SF (1<<3) 1403# define IR_SF (1 << 3)
1408# define IR_SIR (1<<4) 1404# define IR_SIR (1 << 4)
1409# define IR_MIR (1<<5) 1405# define IR_MIR (1 << 5)
1410# define IR_FIR (1<<6) 1406# define IR_FIR (1 << 6)
1411# define IR_16CRC (1<<7) 1407# define IR_16CRC (1 << 7)
1412# define IR_TD (1<<8) 1408# define IR_TD (1 << 8)
1413# define IR_RX_ALL (1<<9) 1409# define IR_RX_ALL (1 << 9)
1414# define IR_DMA_ENABLE (1<<10) 1410# define IR_DMA_ENABLE (1 << 10)
1415# define IR_RX_ENABLE (1<<11) 1411# define IR_RX_ENABLE (1 << 11)
1416# define IR_TX_ENABLE (1<<12) 1412# define IR_TX_ENABLE (1 << 12)
1417# define IR_LOOPBACK (1<<14) 1413# define IR_LOOPBACK (1 << 14)
1418# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ 1414# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1419 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) 1415 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1420#define IR_SIR_FLAGS (IRDA_BASE+0x24) 1416#define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1421#define IR_ENABLE (IRDA_BASE+0x28) 1417#define IR_ENABLE (IRDA_BASE + 0x28)
1422# define IR_RX_STATUS (1<<9) 1418# define IR_RX_STATUS (1 << 9)
1423# define IR_TX_STATUS (1<<10) 1419# define IR_TX_STATUS (1 << 10)
1424#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) 1420#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1425#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) 1421#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1426#define IR_MAX_PKT_LEN (IRDA_BASE+0x34) 1422#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1427#define IR_RX_BYTE_CNT (IRDA_BASE+0x38) 1423#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1428#define IR_CONFIG_2 (IRDA_BASE+0x3C) 1424#define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1429# define IR_MODE_INV (1<<0) 1425# define IR_MODE_INV (1 << 0)
1430# define IR_ONE_PIN (1<<1) 1426# define IR_ONE_PIN (1 << 1)
1431#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) 1427#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1432 1428
1433/* GPIO */ 1429/* GPIO */
1434#define SYS_PINFUNC 0xB190002C 1430#define SYS_PINFUNC 0xB190002C
1435# define SYS_PF_USB (1<<15) /* 2nd USB device/host */ 1431# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1436# define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ 1432# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1437# define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ 1433# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1438# define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ 1434# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1439# define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ 1435# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1440# define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ 1436# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1441# define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ 1437# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1442# define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ 1438# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1443# define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ 1439# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1444# define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ 1440# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1445# define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ 1441# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1446# define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ 1442# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1447# define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ 1443# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1448# define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ 1444# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1449# define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ 1445# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1450# define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ 1446# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1451 1447
1452/* Au1100 Only */ 1448/* Au1100 only */
1453# define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ 1449# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1454# define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ 1450# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1455# define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ 1451# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1456# define SYS_PF_EX0 (1<<9) /* gpio2/clock */ 1452# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1457 1453
1458/* Au1550 Only. Redefines lots of pins */ 1454/* Au1550 only. Redefines lots of pins */
1459# define SYS_PF_PSC2_MASK (7 << 17) 1455# define SYS_PF_PSC2_MASK (7 << 17)
1460# define SYS_PF_PSC2_AC97 (0) 1456# define SYS_PF_PSC2_AC97 0
1461# define SYS_PF_PSC2_SPI (0) 1457# define SYS_PF_PSC2_SPI 0
1462# define SYS_PF_PSC2_I2S (1 << 17) 1458# define SYS_PF_PSC2_I2S (1 << 17)
1463# define SYS_PF_PSC2_SMBUS (3 << 17) 1459# define SYS_PF_PSC2_SMBUS (3 << 17)
1464# define SYS_PF_PSC2_GPIO (7 << 17) 1460# define SYS_PF_PSC2_GPIO (7 << 17)
1465# define SYS_PF_PSC3_MASK (7 << 20) 1461# define SYS_PF_PSC3_MASK (7 << 20)
1466# define SYS_PF_PSC3_AC97 (0) 1462# define SYS_PF_PSC3_AC97 0
1467# define SYS_PF_PSC3_SPI (0) 1463# define SYS_PF_PSC3_SPI 0
1468# define SYS_PF_PSC3_I2S (1 << 20) 1464# define SYS_PF_PSC3_I2S (1 << 20)
1469# define SYS_PF_PSC3_SMBUS (3 << 20) 1465# define SYS_PF_PSC3_SMBUS (3 << 20)
1470# define SYS_PF_PSC3_GPIO (7 << 20) 1466# define SYS_PF_PSC3_GPIO (7 << 20)
1471# define SYS_PF_PSC1_S1 (1 << 1) 1467# define SYS_PF_PSC1_S1 (1 << 1)
1472# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1468# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1473 1469
1474/* Au1200 Only */ 1470/* Au1200 only */
1475#ifdef CONFIG_SOC_AU1200 1471#ifdef CONFIG_SOC_AU1200
1476#define SYS_PINFUNC_DMA (1<<31) 1472#define SYS_PINFUNC_DMA (1 << 31)
1477#define SYS_PINFUNC_S0A (1<<30) 1473#define SYS_PINFUNC_S0A (1 << 30)
1478#define SYS_PINFUNC_S1A (1<<29) 1474#define SYS_PINFUNC_S1A (1 << 29)
1479#define SYS_PINFUNC_LP0 (1<<28) 1475#define SYS_PINFUNC_LP0 (1 << 28)
1480#define SYS_PINFUNC_LP1 (1<<27) 1476#define SYS_PINFUNC_LP1 (1 << 27)
1481#define SYS_PINFUNC_LD16 (1<<26) 1477#define SYS_PINFUNC_LD16 (1 << 26)
1482#define SYS_PINFUNC_LD8 (1<<25) 1478#define SYS_PINFUNC_LD8 (1 << 25)
1483#define SYS_PINFUNC_LD1 (1<<24) 1479#define SYS_PINFUNC_LD1 (1 << 24)
1484#define SYS_PINFUNC_LD0 (1<<23) 1480#define SYS_PINFUNC_LD0 (1 << 23)
1485#define SYS_PINFUNC_P1A (3<<21) 1481#define SYS_PINFUNC_P1A (3 << 21)
1486#define SYS_PINFUNC_P1B (1<<20) 1482#define SYS_PINFUNC_P1B (1 << 20)
1487#define SYS_PINFUNC_FS3 (1<<19) 1483#define SYS_PINFUNC_FS3 (1 << 19)
1488#define SYS_PINFUNC_P0A (3<<17) 1484#define SYS_PINFUNC_P0A (3 << 17)
1489#define SYS_PINFUNC_CS (1<<16) 1485#define SYS_PINFUNC_CS (1 << 16)
1490#define SYS_PINFUNC_CIM (1<<15) 1486#define SYS_PINFUNC_CIM (1 << 15)
1491#define SYS_PINFUNC_P1C (1<<14) 1487#define SYS_PINFUNC_P1C (1 << 14)
1492#define SYS_PINFUNC_U1T (1<<12) 1488#define SYS_PINFUNC_U1T (1 << 12)
1493#define SYS_PINFUNC_U1R (1<<11) 1489#define SYS_PINFUNC_U1R (1 << 11)
1494#define SYS_PINFUNC_EX1 (1<<10) 1490#define SYS_PINFUNC_EX1 (1 << 10)
1495#define SYS_PINFUNC_EX0 (1<<9) 1491#define SYS_PINFUNC_EX0 (1 << 9)
1496#define SYS_PINFUNC_U0R (1<<8) 1492#define SYS_PINFUNC_U0R (1 << 8)
1497#define SYS_PINFUNC_MC (1<<7) 1493#define SYS_PINFUNC_MC (1 << 7)
1498#define SYS_PINFUNC_S0B (1<<6) 1494#define SYS_PINFUNC_S0B (1 << 6)
1499#define SYS_PINFUNC_S0C (1<<5) 1495#define SYS_PINFUNC_S0C (1 << 5)
1500#define SYS_PINFUNC_P0B (1<<4) 1496#define SYS_PINFUNC_P0B (1 << 4)
1501#define SYS_PINFUNC_U0T (1<<3) 1497#define SYS_PINFUNC_U0T (1 << 3)
1502#define SYS_PINFUNC_S1B (1<<2) 1498#define SYS_PINFUNC_S1B (1 << 2)
1503#endif 1499#endif
1504 1500
1505#define SYS_TRIOUTRD 0xB1900100 1501#define SYS_TRIOUTRD 0xB1900100
1506#define SYS_TRIOUTCLR 0xB1900100 1502#define SYS_TRIOUTCLR 0xB1900100
1507#define SYS_OUTPUTRD 0xB1900108 1503#define SYS_OUTPUTRD 0xB1900108
1508#define SYS_OUTPUTSET 0xB1900108 1504#define SYS_OUTPUTSET 0xB1900108
1509#define SYS_OUTPUTCLR 0xB190010C 1505#define SYS_OUTPUTCLR 0xB190010C
1510#define SYS_PINSTATERD 0xB1900110 1506#define SYS_PINSTATERD 0xB1900110
1511#define SYS_PININPUTEN 0xB1900110 1507#define SYS_PININPUTEN 0xB1900110
1512 1508
1513/* GPIO2, Au1500, Au1550 only */ 1509/* GPIO2, Au1500, Au1550 only */
1514#define GPIO2_BASE 0xB1700000 1510#define GPIO2_BASE 0xB1700000
1515#define GPIO2_DIR (GPIO2_BASE + 0) 1511#define GPIO2_DIR (GPIO2_BASE + 0)
1516#define GPIO2_OUTPUT (GPIO2_BASE + 8) 1512#define GPIO2_OUTPUT (GPIO2_BASE + 8)
1517#define GPIO2_PINSTATE (GPIO2_BASE + 0xC) 1513#define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1518#define GPIO2_INTENABLE (GPIO2_BASE + 0x10) 1514#define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1519#define GPIO2_ENABLE (GPIO2_BASE + 0x14) 1515#define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1520 1516
1521/* Power Management */ 1517/* Power Management */
1522#define SYS_SCRATCH0 0xB1900018 1518#define SYS_SCRATCH0 0xB1900018
1523#define SYS_SCRATCH1 0xB190001C 1519#define SYS_SCRATCH1 0xB190001C
1524#define SYS_WAKEMSK 0xB1900034 1520#define SYS_WAKEMSK 0xB1900034
1525#define SYS_ENDIAN 0xB1900038 1521#define SYS_ENDIAN 0xB1900038
1526#define SYS_POWERCTRL 0xB190003C 1522#define SYS_POWERCTRL 0xB190003C
1527#define SYS_WAKESRC 0xB190005C 1523#define SYS_WAKESRC 0xB190005C
1528#define SYS_SLPPWR 0xB1900078 1524#define SYS_SLPPWR 0xB1900078
1529#define SYS_SLEEP 0xB190007C 1525#define SYS_SLEEP 0xB190007C
1530 1526
1531/* Clock Controller */ 1527/* Clock Controller */
1532#define SYS_FREQCTRL0 0xB1900020 1528#define SYS_FREQCTRL0 0xB1900020
1533# define SYS_FC_FRDIV2_BIT 22 1529# define SYS_FC_FRDIV2_BIT 22
1534# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) 1530# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1535# define SYS_FC_FE2 (1<<21) 1531# define SYS_FC_FE2 (1 << 21)
1536# define SYS_FC_FS2 (1<<20) 1532# define SYS_FC_FS2 (1 << 20)
1537# define SYS_FC_FRDIV1_BIT 12 1533# define SYS_FC_FRDIV1_BIT 12
1538# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) 1534# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1539# define SYS_FC_FE1 (1<<11) 1535# define SYS_FC_FE1 (1 << 11)
1540# define SYS_FC_FS1 (1<<10) 1536# define SYS_FC_FS1 (1 << 10)
1541# define SYS_FC_FRDIV0_BIT 2 1537# define SYS_FC_FRDIV0_BIT 2
1542# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) 1538# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1543# define SYS_FC_FE0 (1<<1) 1539# define SYS_FC_FE0 (1 << 1)
1544# define SYS_FC_FS0 (1<<0) 1540# define SYS_FC_FS0 (1 << 0)
1545#define SYS_FREQCTRL1 0xB1900024 1541#define SYS_FREQCTRL1 0xB1900024
1546# define SYS_FC_FRDIV5_BIT 22 1542# define SYS_FC_FRDIV5_BIT 22
1547# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) 1543# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1548# define SYS_FC_FE5 (1<<21) 1544# define SYS_FC_FE5 (1 << 21)
1549# define SYS_FC_FS5 (1<<20) 1545# define SYS_FC_FS5 (1 << 20)
1550# define SYS_FC_FRDIV4_BIT 12 1546# define SYS_FC_FRDIV4_BIT 12
1551# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) 1547# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1552# define SYS_FC_FE4 (1<<11) 1548# define SYS_FC_FE4 (1 << 11)
1553# define SYS_FC_FS4 (1<<10) 1549# define SYS_FC_FS4 (1 << 10)
1554# define SYS_FC_FRDIV3_BIT 2 1550# define SYS_FC_FRDIV3_BIT 2
1555# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) 1551# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1556# define SYS_FC_FE3 (1<<1) 1552# define SYS_FC_FE3 (1 << 1)
1557# define SYS_FC_FS3 (1<<0) 1553# define SYS_FC_FS3 (1 << 0)
1558#define SYS_CLKSRC 0xB1900028 1554#define SYS_CLKSRC 0xB1900028
1559# define SYS_CS_ME1_BIT 27 1555# define SYS_CS_ME1_BIT 27
1560# define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) 1556# define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1561# define SYS_CS_DE1 (1<<26) 1557# define SYS_CS_DE1 (1 << 26)
1562# define SYS_CS_CE1 (1<<25) 1558# define SYS_CS_CE1 (1 << 25)
1563# define SYS_CS_ME0_BIT 22 1559# define SYS_CS_ME0_BIT 22
1564# define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) 1560# define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1565# define SYS_CS_DE0 (1<<21) 1561# define SYS_CS_DE0 (1 << 21)
1566# define SYS_CS_CE0 (1<<20) 1562# define SYS_CS_CE0 (1 << 20)
1567# define SYS_CS_MI2_BIT 17 1563# define SYS_CS_MI2_BIT 17
1568# define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) 1564# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1569# define SYS_CS_DI2 (1<<16) 1565# define SYS_CS_DI2 (1 << 16)
1570# define SYS_CS_CI2 (1<<15) 1566# define SYS_CS_CI2 (1 << 15)
1571#ifdef CONFIG_SOC_AU1100 1567#ifdef CONFIG_SOC_AU1100
1572# define SYS_CS_ML_BIT 7 1568# define SYS_CS_ML_BIT 7
1573# define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) 1569# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1574# define SYS_CS_DL (1<<6) 1570# define SYS_CS_DL (1 << 6)
1575# define SYS_CS_CL (1<<5) 1571# define SYS_CS_CL (1 << 5)
1576#else 1572#else
1577# define SYS_CS_MUH_BIT 12 1573# define SYS_CS_MUH_BIT 12
1578# define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) 1574# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1579# define SYS_CS_DUH (1<<11) 1575# define SYS_CS_DUH (1 << 11)
1580# define SYS_CS_CUH (1<<10) 1576# define SYS_CS_CUH (1 << 10)
1581# define SYS_CS_MUD_BIT 7 1577# define SYS_CS_MUD_BIT 7
1582# define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) 1578# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1583# define SYS_CS_DUD (1<<6) 1579# define SYS_CS_DUD (1 << 6)
1584# define SYS_CS_CUD (1<<5) 1580# define SYS_CS_CUD (1 << 5)
1585#endif 1581#endif
1586# define SYS_CS_MIR_BIT 2 1582# define SYS_CS_MIR_BIT 2
1587# define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) 1583# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1588# define SYS_CS_DIR (1<<1) 1584# define SYS_CS_DIR (1 << 1)
1589# define SYS_CS_CIR (1<<0) 1585# define SYS_CS_CIR (1 << 0)
1590 1586
1591# define SYS_CS_MUX_AUX 0x1 1587# define SYS_CS_MUX_AUX 0x1
1592# define SYS_CS_MUX_FQ0 0x2 1588# define SYS_CS_MUX_FQ0 0x2
1593# define SYS_CS_MUX_FQ1 0x3 1589# define SYS_CS_MUX_FQ1 0x3
1594# define SYS_CS_MUX_FQ2 0x4 1590# define SYS_CS_MUX_FQ2 0x4
1595# define SYS_CS_MUX_FQ3 0x5 1591# define SYS_CS_MUX_FQ3 0x5
1596# define SYS_CS_MUX_FQ4 0x6 1592# define SYS_CS_MUX_FQ4 0x6
1597# define SYS_CS_MUX_FQ5 0x7 1593# define SYS_CS_MUX_FQ5 0x7
1598#define SYS_CPUPLL 0xB1900060 1594#define SYS_CPUPLL 0xB1900060
1599#define SYS_AUXPLL 0xB1900064 1595#define SYS_AUXPLL 0xB1900064
1600 1596
1601/* AC97 Controller */ 1597/* AC97 Controller */
1602#define AC97C_CONFIG 0xB0000000 1598#define AC97C_CONFIG 0xB0000000
1603# define AC97C_RECV_SLOTS_BIT 13 1599# define AC97C_RECV_SLOTS_BIT 13
1604# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) 1600# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1605# define AC97C_XMIT_SLOTS_BIT 3 1601# define AC97C_XMIT_SLOTS_BIT 3
1606# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) 1602# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1607# define AC97C_SG (1<<2) 1603# define AC97C_SG (1 << 2)
1608# define AC97C_SYNC (1<<1) 1604# define AC97C_SYNC (1 << 1)
1609# define AC97C_RESET (1<<0) 1605# define AC97C_RESET (1 << 0)
1610#define AC97C_STATUS 0xB0000004 1606#define AC97C_STATUS 0xB0000004
1611# define AC97C_XU (1<<11) 1607# define AC97C_XU (1 << 11)
1612# define AC97C_XO (1<<10) 1608# define AC97C_XO (1 << 10)
1613# define AC97C_RU (1<<9) 1609# define AC97C_RU (1 << 9)
1614# define AC97C_RO (1<<8) 1610# define AC97C_RO (1 << 8)
1615# define AC97C_READY (1<<7) 1611# define AC97C_READY (1 << 7)
1616# define AC97C_CP (1<<6) 1612# define AC97C_CP (1 << 6)
1617# define AC97C_TR (1<<5) 1613# define AC97C_TR (1 << 5)
1618# define AC97C_TE (1<<4) 1614# define AC97C_TE (1 << 4)
1619# define AC97C_TF (1<<3) 1615# define AC97C_TF (1 << 3)
1620# define AC97C_RR (1<<2) 1616# define AC97C_RR (1 << 2)
1621# define AC97C_RE (1<<1) 1617# define AC97C_RE (1 << 1)
1622# define AC97C_RF (1<<0) 1618# define AC97C_RF (1 << 0)
1623#define AC97C_DATA 0xB0000008 1619#define AC97C_DATA 0xB0000008
1624#define AC97C_CMD 0xB000000C 1620#define AC97C_CMD 0xB000000C
1625# define AC97C_WD_BIT 16 1621# define AC97C_WD_BIT 16
1626# define AC97C_READ (1<<7) 1622# define AC97C_READ (1 << 7)
1627# define AC97C_INDEX_MASK 0x7f 1623# define AC97C_INDEX_MASK 0x7f
1628#define AC97C_CNTRL 0xB0000010 1624#define AC97C_CNTRL 0xB0000010
1629# define AC97C_RS (1<<1) 1625# define AC97C_RS (1 << 1)
1630# define AC97C_CE (1<<0) 1626# define AC97C_CE (1 << 0)
1631
1632 1627
1633/* Secure Digital (SD) Controller */ 1628/* Secure Digital (SD) Controller */
1634#define SD0_XMIT_FIFO 0xB0600000 1629#define SD0_XMIT_FIFO 0xB0600000
@@ -1638,73 +1633,74 @@ enum soc_au1200_ints {
1638 1633
1639#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 1634#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1640/* Au1500 PCI Controller */ 1635/* Au1500 PCI Controller */
1641#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr 1636#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
1642#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) 1637#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1643#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) 1638#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1644# define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) 1639# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
1645#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) 1640 (1 << 25) | (1 << 26) | (1 << 27))
1646#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) 1641#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1647#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) 1642#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1648#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) 1643#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1644#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1649#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) 1645#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1650#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) 1646#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1651#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) 1647#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1652#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) 1648#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1653#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) 1649#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1654#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) 1650#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1655#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) 1651#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1656#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) 1652#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1657 1653
1658#define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr 1654#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
1659 1655
1660/* All of our structures, like pci resource, have 32 bit members. 1656/*
1657 * All of our structures, like PCI resource, have 32-bit members.
1661 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's 1658 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1662 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch 1659 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
1663 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and 1660 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1664 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM 1661 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
1665 * addresses. For PCI IO, it's simpler because we get to do the ioremap 1662 * addresses. For PCI I/O, it's simpler because we get to do the ioremap
1666 * ourselves and then adjust the device's resources. 1663 * ourselves and then adjust the device's resources.
1667 */ 1664 */
1668#define Au1500_EXT_CFG 0x600000000ULL 1665#define Au1500_EXT_CFG 0x600000000ULL
1669#define Au1500_EXT_CFG_TYPE1 0x680000000ULL 1666#define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1670#define Au1500_PCI_IO_START 0x500000000ULL 1667#define Au1500_PCI_IO_START 0x500000000ULL
1671#define Au1500_PCI_IO_END 0x5000FFFFFULL 1668#define Au1500_PCI_IO_END 0x5000FFFFFULL
1672#define Au1500_PCI_MEM_START 0x440000000ULL 1669#define Au1500_PCI_MEM_START 0x440000000ULL
1673#define Au1500_PCI_MEM_END 0x44FFFFFFFULL 1670#define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1674 1671
1675#define PCI_IO_START 0x00001000 1672#define PCI_IO_START 0x00001000
1676#define PCI_IO_END 0x000FFFFF 1673#define PCI_IO_END 0x000FFFFF
1677#define PCI_MEM_START 0x40000000 1674#define PCI_MEM_START 0x40000000
1678#define PCI_MEM_END 0x4FFFFFFF 1675#define PCI_MEM_END 0x4FFFFFFF
1679 1676
1680#define PCI_FIRST_DEVFN (0<<3) 1677#define PCI_FIRST_DEVFN (0 << 3)
1681#define PCI_LAST_DEVFN (19<<3) 1678#define PCI_LAST_DEVFN (19 << 3)
1682 1679
1683#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ 1680#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1684#define IOPORT_RESOURCE_END 0xffffffff 1681#define IOPORT_RESOURCE_END 0xffffffff
1685#define IOMEM_RESOURCE_START 0x10000000 1682#define IOMEM_RESOURCE_START 0x10000000
1686#define IOMEM_RESOURCE_END 0xffffffff 1683#define IOMEM_RESOURCE_END 0xffffffff
1687 1684
1688#else /* Au1000 and Au1100 and Au1200 */ 1685#else /* Au1000 and Au1100 and Au1200 */
1689 1686
1690/* don't allow any legacy ports probing */ 1687/* Don't allow any legacy ports probing */
1691#define IOPORT_RESOURCE_START 0x10000000 1688#define IOPORT_RESOURCE_START 0x10000000
1692#define IOPORT_RESOURCE_END 0xffffffff 1689#define IOPORT_RESOURCE_END 0xffffffff
1693#define IOMEM_RESOURCE_START 0x10000000 1690#define IOMEM_RESOURCE_START 0x10000000
1694#define IOMEM_RESOURCE_END 0xffffffff 1691#define IOMEM_RESOURCE_END 0xffffffff
1695 1692
1696#define PCI_IO_START 0 1693#define PCI_IO_START 0
1697#define PCI_IO_END 0 1694#define PCI_IO_END 0
1698#define PCI_MEM_START 0 1695#define PCI_MEM_START 0
1699#define PCI_MEM_END 0 1696#define PCI_MEM_END 0
1700#define PCI_FIRST_DEVFN 0 1697#define PCI_FIRST_DEVFN 0
1701#define PCI_LAST_DEVFN 0 1698#define PCI_LAST_DEVFN 0
1702 1699
1703#endif 1700#endif
1704 1701
1705#ifndef _LANGUAGE_ASSEMBLY 1702#ifndef _LANGUAGE_ASSEMBLY
1706typedef volatile struct 1703typedef volatile struct {
1707{
1708 /* 0x0000 */ u32 toytrim; 1704 /* 0x0000 */ u32 toytrim;
1709 /* 0x0004 */ u32 toywrite; 1705 /* 0x0004 */ u32 toywrite;
1710 /* 0x0008 */ u32 toymatch0; 1706 /* 0x0008 */ u32 toymatch0;
@@ -1746,13 +1742,14 @@ typedef volatile struct
1746 /* 0x010C */ u32 outputclr; 1742 /* 0x010C */ u32 outputclr;
1747 /* 0x0110 */ u32 pinstaterd; 1743 /* 0x0110 */ u32 pinstaterd;
1748#define pininputen pinstaterd 1744#define pininputen pinstaterd
1749
1750} AU1X00_SYS; 1745} AU1X00_SYS;
1751 1746
1752static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE; 1747static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
1753 1748
1754#endif 1749#endif
1755/* Processor information base on prid. 1750
1751/*
1752 * Processor information based on PRID.
1756 * Copied from PowerPC. 1753 * Copied from PowerPC.
1757 */ 1754 */
1758#ifndef _LANGUAGE_ASSEMBLY 1755#ifndef _LANGUAGE_ASSEMBLY
@@ -1767,9 +1764,8 @@ struct cpu_spec {
1767 unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */ 1764 unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */
1768}; 1765};
1769 1766
1770extern struct cpu_spec cpu_specs[]; 1767extern struct cpu_spec cpu_specs[];
1771extern struct cpu_spec *cur_cpu_spec[]; 1768extern struct cpu_spec *cur_cpu_spec[];
1772#endif 1769#endif
1773 1770
1774#endif 1771#endif
1775