diff options
Diffstat (limited to 'include/asm-mips/mach-au1x00/au1000.h')
| -rw-r--r-- | include/asm-mips/mach-au1x00/au1000.h | 622 |
1 files changed, 311 insertions, 311 deletions
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 58fca8a5a9a6..10f613f23c33 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h | |||
| @@ -951,25 +951,25 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; | |||
| 951 | /* Programmable Counters 0 and 1 */ | 951 | /* Programmable Counters 0 and 1 */ |
| 952 | #define SYS_BASE 0xB1900000 | 952 | #define SYS_BASE 0xB1900000 |
| 953 | #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) | 953 | #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) |
| 954 | #define SYS_CNTRL_E1S (1<<23) | 954 | # define SYS_CNTRL_E1S (1<<23) |
| 955 | #define SYS_CNTRL_T1S (1<<20) | 955 | # define SYS_CNTRL_T1S (1<<20) |
| 956 | #define SYS_CNTRL_M21 (1<<19) | 956 | # define SYS_CNTRL_M21 (1<<19) |
| 957 | #define SYS_CNTRL_M11 (1<<18) | 957 | # define SYS_CNTRL_M11 (1<<18) |
| 958 | #define SYS_CNTRL_M01 (1<<17) | 958 | # define SYS_CNTRL_M01 (1<<17) |
| 959 | #define SYS_CNTRL_C1S (1<<16) | 959 | # define SYS_CNTRL_C1S (1<<16) |
| 960 | #define SYS_CNTRL_BP (1<<14) | 960 | # define SYS_CNTRL_BP (1<<14) |
| 961 | #define SYS_CNTRL_EN1 (1<<13) | 961 | # define SYS_CNTRL_EN1 (1<<13) |
| 962 | #define SYS_CNTRL_BT1 (1<<12) | 962 | # define SYS_CNTRL_BT1 (1<<12) |
| 963 | #define SYS_CNTRL_EN0 (1<<11) | 963 | # define SYS_CNTRL_EN0 (1<<11) |
| 964 | #define SYS_CNTRL_BT0 (1<<10) | 964 | # define SYS_CNTRL_BT0 (1<<10) |
| 965 | #define SYS_CNTRL_E0 (1<<8) | 965 | # define SYS_CNTRL_E0 (1<<8) |
| 966 | #define SYS_CNTRL_E0S (1<<7) | 966 | # define SYS_CNTRL_E0S (1<<7) |
| 967 | #define SYS_CNTRL_32S (1<<5) | 967 | # define SYS_CNTRL_32S (1<<5) |
| 968 | #define SYS_CNTRL_T0S (1<<4) | 968 | # define SYS_CNTRL_T0S (1<<4) |
| 969 | #define SYS_CNTRL_M20 (1<<3) | 969 | # define SYS_CNTRL_M20 (1<<3) |
| 970 | #define SYS_CNTRL_M10 (1<<2) | 970 | # define SYS_CNTRL_M10 (1<<2) |
| 971 | #define SYS_CNTRL_M00 (1<<1) | 971 | # define SYS_CNTRL_M00 (1<<1) |
| 972 | #define SYS_CNTRL_C0S (1<<0) | 972 | # define SYS_CNTRL_C0S (1<<0) |
| 973 | 973 | ||
| 974 | /* Programmable Counter 0 Registers */ | 974 | /* Programmable Counter 0 Registers */ |
| 975 | #define SYS_TOYTRIM (SYS_BASE + 0) | 975 | #define SYS_TOYTRIM (SYS_BASE + 0) |
| @@ -989,34 +989,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; | |||
| 989 | 989 | ||
| 990 | /* I2S Controller */ | 990 | /* I2S Controller */ |
| 991 | #define I2S_DATA 0xB1000000 | 991 | #define I2S_DATA 0xB1000000 |
| 992 | #define I2S_DATA_MASK (0xffffff) | 992 | # define I2S_DATA_MASK (0xffffff) |
| 993 | #define I2S_CONFIG 0xB1000004 | 993 | #define I2S_CONFIG 0xB1000004 |
| 994 | #define I2S_CONFIG_XU (1<<25) | 994 | # define I2S_CONFIG_XU (1<<25) |
| 995 | #define I2S_CONFIG_XO (1<<24) | 995 | # define I2S_CONFIG_XO (1<<24) |
| 996 | #define I2S_CONFIG_RU (1<<23) | 996 | # define I2S_CONFIG_RU (1<<23) |
| 997 | #define I2S_CONFIG_RO (1<<22) | 997 | # define I2S_CONFIG_RO (1<<22) |
| 998 | #define I2S_CONFIG_TR (1<<21) | 998 | # define I2S_CONFIG_TR (1<<21) |
| 999 | #define I2S_CONFIG_TE (1<<20) | 999 | # define I2S_CONFIG_TE (1<<20) |
| 1000 | #define I2S_CONFIG_TF (1<<19) | 1000 | # define I2S_CONFIG_TF (1<<19) |
| 1001 | #define I2S_CONFIG_RR (1<<18) | 1001 | # define I2S_CONFIG_RR (1<<18) |
| 1002 | #define I2S_CONFIG_RE (1<<17) | 1002 | # define I2S_CONFIG_RE (1<<17) |
| 1003 | #define I2S_CONFIG_RF (1<<16) | 1003 | # define I2S_CONFIG_RF (1<<16) |
| 1004 | #define I2S_CONFIG_PD (1<<11) | 1004 | # define I2S_CONFIG_PD (1<<11) |
| 1005 | #define I2S_CONFIG_LB (1<<10) | 1005 | # define I2S_CONFIG_LB (1<<10) |
| 1006 | #define I2S_CONFIG_IC (1<<9) | 1006 | # define I2S_CONFIG_IC (1<<9) |
| 1007 | #define I2S_CONFIG_FM_BIT 7 | 1007 | # define I2S_CONFIG_FM_BIT 7 |
| 1008 | #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) | 1008 | # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) |
| 1009 | #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) | 1009 | # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) |
| 1010 | #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) | 1010 | # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) |
| 1011 | #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) | 1011 | # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) |
| 1012 | #define I2S_CONFIG_TN (1<<6) | 1012 | # define I2S_CONFIG_TN (1<<6) |
| 1013 | #define I2S_CONFIG_RN (1<<5) | 1013 | # define I2S_CONFIG_RN (1<<5) |
| 1014 | #define I2S_CONFIG_SZ_BIT 0 | 1014 | # define I2S_CONFIG_SZ_BIT 0 |
| 1015 | #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) | 1015 | # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) |
| 1016 | 1016 | ||
| 1017 | #define I2S_CONTROL 0xB1000008 | 1017 | #define I2S_CONTROL 0xB1000008 |
| 1018 | #define I2S_CONTROL_D (1<<1) | 1018 | # define I2S_CONTROL_D (1<<1) |
| 1019 | #define I2S_CONTROL_CE (1<<0) | 1019 | # define I2S_CONTROL_CE (1<<0) |
| 1020 | 1020 | ||
| 1021 | /* USB Host Controller */ | 1021 | /* USB Host Controller */ |
| 1022 | #ifndef USB_OHCI_LEN | 1022 | #ifndef USB_OHCI_LEN |
| @@ -1034,38 +1034,38 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; | |||
| 1034 | #define USBD_EP5RD 0xB0200014 | 1034 | #define USBD_EP5RD 0xB0200014 |
| 1035 | #define USBD_INTEN 0xB0200018 | 1035 | #define USBD_INTEN 0xB0200018 |
| 1036 | #define USBD_INTSTAT 0xB020001C | 1036 | #define USBD_INTSTAT 0xB020001C |
| 1037 | #define USBDEV_INT_SOF (1<<12) | 1037 | # define USBDEV_INT_SOF (1<<12) |
| 1038 | #define USBDEV_INT_HF_BIT 6 | 1038 | # define USBDEV_INT_HF_BIT 6 |
| 1039 | #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) | 1039 | # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) |
| 1040 | #define USBDEV_INT_CMPLT_BIT 0 | 1040 | # define USBDEV_INT_CMPLT_BIT 0 |
| 1041 | #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) | 1041 | # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) |
| 1042 | #define USBD_CONFIG 0xB0200020 | 1042 | #define USBD_CONFIG 0xB0200020 |
| 1043 | #define USBD_EP0CS 0xB0200024 | 1043 | #define USBD_EP0CS 0xB0200024 |
| 1044 | #define USBD_EP2CS 0xB0200028 | 1044 | #define USBD_EP2CS 0xB0200028 |
| 1045 | #define USBD_EP3CS 0xB020002C | 1045 | #define USBD_EP3CS 0xB020002C |
| 1046 | #define USBD_EP4CS 0xB0200030 | 1046 | #define USBD_EP4CS 0xB0200030 |
| 1047 | #define USBD_EP5CS 0xB0200034 | 1047 | #define USBD_EP5CS 0xB0200034 |
| 1048 | #define USBDEV_CS_SU (1<<14) | 1048 | # define USBDEV_CS_SU (1<<14) |
| 1049 | #define USBDEV_CS_NAK (1<<13) | 1049 | # define USBDEV_CS_NAK (1<<13) |
| 1050 | #define USBDEV_CS_ACK (1<<12) | 1050 | # define USBDEV_CS_ACK (1<<12) |
| 1051 | #define USBDEV_CS_BUSY (1<<11) | 1051 | # define USBDEV_CS_BUSY (1<<11) |
| 1052 | #define USBDEV_CS_TSIZE_BIT 1 | 1052 | # define USBDEV_CS_TSIZE_BIT 1 |
| 1053 | #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) | 1053 | # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) |
| 1054 | #define USBDEV_CS_STALL (1<<0) | 1054 | # define USBDEV_CS_STALL (1<<0) |
| 1055 | #define USBD_EP0RDSTAT 0xB0200040 | 1055 | #define USBD_EP0RDSTAT 0xB0200040 |
| 1056 | #define USBD_EP0WRSTAT 0xB0200044 | 1056 | #define USBD_EP0WRSTAT 0xB0200044 |
| 1057 | #define USBD_EP2WRSTAT 0xB0200048 | 1057 | #define USBD_EP2WRSTAT 0xB0200048 |
| 1058 | #define USBD_EP3WRSTAT 0xB020004C | 1058 | #define USBD_EP3WRSTAT 0xB020004C |
| 1059 | #define USBD_EP4RDSTAT 0xB0200050 | 1059 | #define USBD_EP4RDSTAT 0xB0200050 |
| 1060 | #define USBD_EP5RDSTAT 0xB0200054 | 1060 | #define USBD_EP5RDSTAT 0xB0200054 |
| 1061 | #define USBDEV_FSTAT_FLUSH (1<<6) | 1061 | # define USBDEV_FSTAT_FLUSH (1<<6) |
| 1062 | #define USBDEV_FSTAT_UF (1<<5) | 1062 | # define USBDEV_FSTAT_UF (1<<5) |
| 1063 | #define USBDEV_FSTAT_OF (1<<4) | 1063 | # define USBDEV_FSTAT_OF (1<<4) |
| 1064 | #define USBDEV_FSTAT_FCNT_BIT 0 | 1064 | # define USBDEV_FSTAT_FCNT_BIT 0 |
| 1065 | #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) | 1065 | # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) |
| 1066 | #define USBD_ENABLE 0xB0200058 | 1066 | #define USBD_ENABLE 0xB0200058 |
| 1067 | #define USBDEV_ENABLE (1<<1) | 1067 | # define USBDEV_ENABLE (1<<1) |
| 1068 | #define USBDEV_CE (1<<0) | 1068 | # define USBDEV_CE (1<<0) |
| 1069 | 1069 | ||
| 1070 | #endif /* !CONFIG_SOC_AU1200 */ | 1070 | #endif /* !CONFIG_SOC_AU1200 */ |
| 1071 | 1071 | ||
| @@ -1073,55 +1073,55 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; | |||
| 1073 | 1073 | ||
| 1074 | /* 4 byte offsets from AU1000_ETH_BASE */ | 1074 | /* 4 byte offsets from AU1000_ETH_BASE */ |
| 1075 | #define MAC_CONTROL 0x0 | 1075 | #define MAC_CONTROL 0x0 |
| 1076 | #define MAC_RX_ENABLE (1<<2) | 1076 | # define MAC_RX_ENABLE (1<<2) |
| 1077 | #define MAC_TX_ENABLE (1<<3) | 1077 | # define MAC_TX_ENABLE (1<<3) |
| 1078 | #define MAC_DEF_CHECK (1<<5) | 1078 | # define MAC_DEF_CHECK (1<<5) |
| 1079 | #define MAC_SET_BL(X) (((X)&0x3)<<6) | 1079 | # define MAC_SET_BL(X) (((X)&0x3)<<6) |
| 1080 | #define MAC_AUTO_PAD (1<<8) | 1080 | # define MAC_AUTO_PAD (1<<8) |
| 1081 | #define MAC_DISABLE_RETRY (1<<10) | 1081 | # define MAC_DISABLE_RETRY (1<<10) |
| 1082 | #define MAC_DISABLE_BCAST (1<<11) | 1082 | # define MAC_DISABLE_BCAST (1<<11) |
| 1083 | #define MAC_LATE_COL (1<<12) | 1083 | # define MAC_LATE_COL (1<<12) |
| 1084 | #define MAC_HASH_MODE (1<<13) | 1084 | # define MAC_HASH_MODE (1<<13) |
| 1085 | #define MAC_HASH_ONLY (1<<15) | 1085 | # define MAC_HASH_ONLY (1<<15) |
| 1086 | #define MAC_PASS_ALL (1<<16) | 1086 | # define MAC_PASS_ALL (1<<16) |
| 1087 | #define MAC_INVERSE_FILTER (1<<17) | 1087 | # define MAC_INVERSE_FILTER (1<<17) |
| 1088 | #define MAC_PROMISCUOUS (1<<18) | 1088 | # define MAC_PROMISCUOUS (1<<18) |
| 1089 | #define MAC_PASS_ALL_MULTI (1<<19) | 1089 | # define MAC_PASS_ALL_MULTI (1<<19) |
| 1090 | #define MAC_FULL_DUPLEX (1<<20) | 1090 | # define MAC_FULL_DUPLEX (1<<20) |
| 1091 | #define MAC_NORMAL_MODE 0 | 1091 | # define MAC_NORMAL_MODE 0 |
| 1092 | #define MAC_INT_LOOPBACK (1<<21) | 1092 | # define MAC_INT_LOOPBACK (1<<21) |
| 1093 | #define MAC_EXT_LOOPBACK (1<<22) | 1093 | # define MAC_EXT_LOOPBACK (1<<22) |
| 1094 | #define MAC_DISABLE_RX_OWN (1<<23) | 1094 | # define MAC_DISABLE_RX_OWN (1<<23) |
| 1095 | #define MAC_BIG_ENDIAN (1<<30) | 1095 | # define MAC_BIG_ENDIAN (1<<30) |
| 1096 | #define MAC_RX_ALL (1<<31) | 1096 | # define MAC_RX_ALL (1<<31) |
| 1097 | #define MAC_ADDRESS_HIGH 0x4 | 1097 | #define MAC_ADDRESS_HIGH 0x4 |
| 1098 | #define MAC_ADDRESS_LOW 0x8 | 1098 | #define MAC_ADDRESS_LOW 0x8 |
| 1099 | #define MAC_MCAST_HIGH 0xC | 1099 | #define MAC_MCAST_HIGH 0xC |
| 1100 | #define MAC_MCAST_LOW 0x10 | 1100 | #define MAC_MCAST_LOW 0x10 |
| 1101 | #define MAC_MII_CNTRL 0x14 | 1101 | #define MAC_MII_CNTRL 0x14 |
| 1102 | #define MAC_MII_BUSY (1<<0) | 1102 | # define MAC_MII_BUSY (1<<0) |
| 1103 | #define MAC_MII_READ 0 | 1103 | # define MAC_MII_READ 0 |
| 1104 | #define MAC_MII_WRITE (1<<1) | 1104 | # define MAC_MII_WRITE (1<<1) |
| 1105 | #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) | 1105 | # define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) |
| 1106 | #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) | 1106 | # define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) |
| 1107 | #define MAC_MII_DATA 0x18 | 1107 | #define MAC_MII_DATA 0x18 |
| 1108 | #define MAC_FLOW_CNTRL 0x1C | 1108 | #define MAC_FLOW_CNTRL 0x1C |
| 1109 | #define MAC_FLOW_CNTRL_BUSY (1<<0) | 1109 | # define MAC_FLOW_CNTRL_BUSY (1<<0) |
| 1110 | #define MAC_FLOW_CNTRL_ENABLE (1<<1) | 1110 | # define MAC_FLOW_CNTRL_ENABLE (1<<1) |
| 1111 | #define MAC_PASS_CONTROL (1<<2) | 1111 | # define MAC_PASS_CONTROL (1<<2) |
| 1112 | #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) | 1112 | # define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) |
| 1113 | #define MAC_VLAN1_TAG 0x20 | 1113 | #define MAC_VLAN1_TAG 0x20 |
| 1114 | #define MAC_VLAN2_TAG 0x24 | 1114 | #define MAC_VLAN2_TAG 0x24 |
| 1115 | 1115 | ||
| 1116 | /* Ethernet Controller Enable */ | 1116 | /* Ethernet Controller Enable */ |
| 1117 | 1117 | ||
| 1118 | #define MAC_EN_CLOCK_ENABLE (1<<0) | 1118 | # define MAC_EN_CLOCK_ENABLE (1<<0) |
| 1119 | #define MAC_EN_RESET0 (1<<1) | 1119 | # define MAC_EN_RESET0 (1<<1) |
| 1120 | #define MAC_EN_TOSS (0<<2) | 1120 | # define MAC_EN_TOSS (0<<2) |
| 1121 | #define MAC_EN_CACHEABLE (1<<3) | 1121 | # define MAC_EN_CACHEABLE (1<<3) |
| 1122 | #define MAC_EN_RESET1 (1<<4) | 1122 | # define MAC_EN_RESET1 (1<<4) |
| 1123 | #define MAC_EN_RESET2 (1<<5) | 1123 | # define MAC_EN_RESET2 (1<<5) |
| 1124 | #define MAC_DMA_RESET (1<<6) | 1124 | # define MAC_DMA_RESET (1<<6) |
| 1125 | 1125 | ||
| 1126 | /* Ethernet Controller DMA Channels */ | 1126 | /* Ethernet Controller DMA Channels */ |
| 1127 | 1127 | ||
| @@ -1129,22 +1129,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; | |||
| 1129 | #define MAC1_TX_DMA_ADDR 0xB4004200 | 1129 | #define MAC1_TX_DMA_ADDR 0xB4004200 |
| 1130 | /* offsets from MAC_TX_RING_ADDR address */ | 1130 | /* offsets from MAC_TX_RING_ADDR address */ |
| 1131 | #define MAC_TX_BUFF0_STATUS 0x0 | 1131 | #define MAC_TX_BUFF0_STATUS 0x0 |
| 1132 | #define TX_FRAME_ABORTED (1<<0) | 1132 | # define TX_FRAME_ABORTED (1<<0) |
| 1133 | #define TX_JAB_TIMEOUT (1<<1) | 1133 | # define TX_JAB_TIMEOUT (1<<1) |
| 1134 | #define TX_NO_CARRIER (1<<2) | 1134 | # define TX_NO_CARRIER (1<<2) |
| 1135 | #define TX_LOSS_CARRIER (1<<3) | 1135 | # define TX_LOSS_CARRIER (1<<3) |
| 1136 | #define TX_EXC_DEF (1<<4) | 1136 | # define TX_EXC_DEF (1<<4) |
| 1137 | #define TX_LATE_COLL_ABORT (1<<5) | 1137 | # define TX_LATE_COLL_ABORT (1<<5) |
| 1138 | #define TX_EXC_COLL (1<<6) | 1138 | # define TX_EXC_COLL (1<<6) |
| 1139 | #define TX_UNDERRUN (1<<7) | 1139 | # define TX_UNDERRUN (1<<7) |
| 1140 | #define TX_DEFERRED (1<<8) | 1140 | # define TX_DEFERRED (1<<8) |
| 1141 | #define TX_LATE_COLL (1<<9) | 1141 | # define TX_LATE_COLL (1<<9) |
| 1142 | #define TX_COLL_CNT_MASK (0xF<<10) | 1142 | # define TX_COLL_CNT_MASK (0xF<<10) |
| 1143 | #define TX_PKT_RETRY (1<<31) | 1143 | # define TX_PKT_RETRY (1<<31) |
| 1144 | #define MAC_TX_BUFF0_ADDR 0x4 | 1144 | #define MAC_TX_BUFF0_ADDR 0x4 |
| 1145 | #define TX_DMA_ENABLE (1<<0) | 1145 | # define TX_DMA_ENABLE (1<<0) |
| 1146 | #define TX_T_DONE (1<<1) | 1146 | # define TX_T_DONE (1<<1) |
| 1147 | #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) | 1147 | # define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) |
| 1148 | #define MAC_TX_BUFF0_LEN 0x8 | 1148 | #define MAC_TX_BUFF0_LEN 0x8 |
| 1149 | #define MAC_TX_BUFF1_STATUS 0x10 | 1149 | #define MAC_TX_BUFF1_STATUS 0x10 |
| 1150 | #define MAC_TX_BUFF1_ADDR 0x14 | 1150 | #define MAC_TX_BUFF1_ADDR 0x14 |
| @@ -1160,34 +1160,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; | |||
| 1160 | #define MAC1_RX_DMA_ADDR 0xB4004300 | 1160 | #define MAC1_RX_DMA_ADDR 0xB4004300 |
| 1161 | /* offsets from MAC_RX_RING_ADDR */ | 1161 | /* offsets from MAC_RX_RING_ADDR */ |
| 1162 | #define MAC_RX_BUFF0_STATUS 0x0 | 1162 | #define MAC_RX_BUFF0_STATUS 0x0 |
| 1163 | #define RX_FRAME_LEN_MASK 0x3fff | 1163 | # define RX_FRAME_LEN_MASK 0x3fff |
| 1164 | #define RX_WDOG_TIMER (1<<14) | 1164 | # define RX_WDOG_TIMER (1<<14) |
| 1165 | #define RX_RUNT (1<<15) | 1165 | # define RX_RUNT (1<<15) |
| 1166 | #define RX_OVERLEN (1<<16) | 1166 | # define RX_OVERLEN (1<<16) |
| 1167 | #define RX_COLL (1<<17) | 1167 | # define RX_COLL (1<<17) |
| 1168 | #define RX_ETHER (1<<18) | 1168 | # define RX_ETHER (1<<18) |
| 1169 | #define RX_MII_ERROR (1<<19) | 1169 | # define RX_MII_ERROR (1<<19) |
| 1170 | #define RX_DRIBBLING (1<<20) | 1170 | # define RX_DRIBBLING (1<<20) |
| 1171 | #define RX_CRC_ERROR (1<<21) | 1171 | # define RX_CRC_ERROR (1<<21) |
| 1172 | #define RX_VLAN1 (1<<22) | 1172 | # define RX_VLAN1 (1<<22) |
| 1173 | #define RX_VLAN2 (1<<23) | 1173 | # define RX_VLAN2 (1<<23) |
| 1174 | #define RX_LEN_ERROR (1<<24) | 1174 | # define RX_LEN_ERROR (1<<24) |
| 1175 | #define RX_CNTRL_FRAME (1<<25) | 1175 | # define RX_CNTRL_FRAME (1<<25) |
| 1176 | #define RX_U_CNTRL_FRAME (1<<26) | 1176 | # define RX_U_CNTRL_FRAME (1<<26) |
| 1177 | #define RX_MCAST_FRAME (1<<27) | 1177 | # define RX_MCAST_FRAME (1<<27) |
| 1178 | #define RX_BCAST_FRAME (1<<28) | 1178 | # define RX_BCAST_FRAME (1<<28) |
| 1179 | #define RX_FILTER_FAIL (1<<29) | 1179 | # define RX_FILTER_FAIL (1<<29) |
| 1180 | #define RX_PACKET_FILTER (1<<30) | 1180 | # define RX_PACKET_FILTER (1<<30) |
| 1181 | #define RX_MISSED_FRAME (1<<31) | 1181 | # define RX_MISSED_FRAME (1<<31) |
| 1182 | 1182 | ||
| 1183 | #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ | 1183 | # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ |
| 1184 | RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ | 1184 | RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ |
| 1185 | RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) | 1185 | RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) |
| 1186 | #define MAC_RX_BUFF0_ADDR 0x4 | 1186 | #define MAC_RX_BUFF0_ADDR 0x4 |
| 1187 | #define RX_DMA_ENABLE (1<<0) | 1187 | # define RX_DMA_ENABLE (1<<0) |
| 1188 | #define RX_T_DONE (1<<1) | 1188 | # define RX_T_DONE (1<<1) |
| 1189 | #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) | 1189 | # define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) |
| 1190 | #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) | 1190 | # define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) |
| 1191 | #define MAC_RX_BUFF1_STATUS 0x10 | 1191 | #define MAC_RX_BUFF1_STATUS 0x10 |
| 1192 | #define MAC_RX_BUFF1_ADDR 0x14 | 1192 | #define MAC_RX_BUFF1_ADDR 0x14 |
| 1193 | #define MAC_RX_BUFF2_STATUS 0x20 | 1193 | #define MAC_RX_BUFF2_STATUS 0x20 |
| @@ -1298,44 +1298,44 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; | |||
| 1298 | 1298 | ||
| 1299 | /* SSIO */ | 1299 | /* SSIO */ |
| 1300 | #define SSI0_STATUS 0xB1600000 | 1300 | #define SSI0_STATUS 0xB1600000 |
| 1301 | #define SSI_STATUS_BF (1<<4) | 1301 | # define SSI_STATUS_BF (1<<4) |
| 1302 | #define SSI_STATUS_OF (1<<3) | 1302 | # define SSI_STATUS_OF (1<<3) |
| 1303 | #define SSI_STATUS_UF (1<<2) | 1303 | # define SSI_STATUS_UF (1<<2) |
| 1304 | #define SSI_STATUS_D (1<<1) | 1304 | # define SSI_STATUS_D (1<<1) |
| 1305 | #define SSI_STATUS_B (1<<0) | 1305 | # define SSI_STATUS_B (1<<0) |
| 1306 | #define SSI0_INT 0xB1600004 | 1306 | #define SSI0_INT 0xB1600004 |
| 1307 | #define SSI_INT_OI (1<<3) | 1307 | # define SSI_INT_OI (1<<3) |
| 1308 | #define SSI_INT_UI (1<<2) | 1308 | # define SSI_INT_UI (1<<2) |
| 1309 | #define SSI_INT_DI (1<<1) | 1309 | # define SSI_INT_DI (1<<1) |
| 1310 | #define SSI0_INT_ENABLE 0xB1600008 | 1310 | #define SSI0_INT_ENABLE 0xB1600008 |
| 1311 | #define SSI_INTE_OIE (1<<3) | 1311 | # define SSI_INTE_OIE (1<<3) |
| 1312 | #define SSI_INTE_UIE (1<<2) | 1312 | # define SSI_INTE_UIE (1<<2) |
| 1313 | #define SSI_INTE_DIE (1<<1) | 1313 | # define SSI_INTE_DIE (1<<1) |
| 1314 | #define SSI0_CONFIG 0xB1600020 | 1314 | #define SSI0_CONFIG 0xB1600020 |
| 1315 | #define SSI_CONFIG_AO (1<<24) | 1315 | # define SSI_CONFIG_AO (1<<24) |
| 1316 | #define SSI_CONFIG_DO (1<<23) | 1316 | # define SSI_CONFIG_DO (1<<23) |
| 1317 | #define SSI_CONFIG_ALEN_BIT 20 | 1317 | # define SSI_CONFIG_ALEN_BIT 20 |
| 1318 | #define SSI_CONFIG_ALEN_MASK (0x7<<20) | 1318 | # define SSI_CONFIG_ALEN_MASK (0x7<<20) |
| 1319 | #define SSI_CONFIG_DLEN_BIT 16 | 1319 | # define SSI_CONFIG_DLEN_BIT 16 |
| 1320 | #define SSI_CONFIG_DLEN_MASK (0x7<<16) | 1320 | # define SSI_CONFIG_DLEN_MASK (0x7<<16) |
| 1321 | #define SSI_CONFIG_DD (1<<11) | 1321 | # define SSI_CONFIG_DD (1<<11) |
| 1322 | #define SSI_CONFIG_AD (1<<10) | 1322 | # define SSI_CONFIG_AD (1<<10) |
| 1323 | #define SSI_CONFIG_BM_BIT 8 | 1323 | # define SSI_CONFIG_BM_BIT 8 |
| 1324 | #define SSI_CONFIG_BM_MASK (0x3<<8) | 1324 | # define SSI_CONFIG_BM_MASK (0x3<<8) |
| 1325 | #define SSI_CONFIG_CE (1<<7) | 1325 | # define SSI_CONFIG_CE (1<<7) |
| 1326 | #define SSI_CONFIG_DP (1<<6) | 1326 | # define SSI_CONFIG_DP (1<<6) |
| 1327 | #define SSI_CONFIG_DL (1<<5) | 1327 | # define SSI_CONFIG_DL (1<<5) |
| 1328 | #define SSI_CONFIG_EP (1<<4) | 1328 | # define SSI_CONFIG_EP (1<<4) |
| 1329 | #define SSI0_ADATA 0xB1600024 | 1329 | #define SSI0_ADATA 0xB1600024 |
| 1330 | #define SSI_AD_D (1<<24) | 1330 | # define SSI_AD_D (1<<24) |
| 1331 | #define SSI_AD_ADDR_BIT 16 | 1331 | # define SSI_AD_ADDR_BIT 16 |
| 1332 | #define SSI_AD_ADDR_MASK (0xff<<16) | 1332 | # define SSI_AD_ADDR_MASK (0xff<<16) |
| 1333 | #define SSI_AD_DATA_BIT 0 | 1333 | # define SSI_AD_DATA_BIT 0 |
| 1334 | #define SSI_AD_DATA_MASK (0xfff<<0) | 1334 | # define SSI_AD_DATA_MASK (0xfff<<0) |
| 1335 | #define SSI0_CLKDIV 0xB1600028 | 1335 | #define SSI0_CLKDIV 0xB1600028 |
| 1336 | #define SSI0_CONTROL 0xB1600100 | 1336 | #define SSI0_CONTROL 0xB1600100 |
| 1337 | #define SSI_CONTROL_CD (1<<1) | 1337 | # define SSI_CONTROL_CD (1<<1) |
| 1338 | #define SSI_CONTROL_E (1<<0) | 1338 | # define SSI_CONTROL_E (1<<0) |
| 1339 | 1339 | ||
| 1340 | /* SSI1 */ | 1340 | /* SSI1 */ |
| 1341 | #define SSI1_STATUS 0xB1680000 | 1341 | #define SSI1_STATUS 0xB1680000 |
| @@ -1401,75 +1401,75 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; | |||
| 1401 | #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) | 1401 | #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) |
| 1402 | #define IR_INT_CLEAR (IRDA_BASE+0x18) | 1402 | #define IR_INT_CLEAR (IRDA_BASE+0x18) |
| 1403 | #define IR_CONFIG_1 (IRDA_BASE+0x20) | 1403 | #define IR_CONFIG_1 (IRDA_BASE+0x20) |
| 1404 | #define IR_RX_INVERT_LED (1<<0) | 1404 | # define IR_RX_INVERT_LED (1<<0) |
| 1405 | #define IR_TX_INVERT_LED (1<<1) | 1405 | # define IR_TX_INVERT_LED (1<<1) |
| 1406 | #define IR_ST (1<<2) | 1406 | # define IR_ST (1<<2) |
| 1407 | #define IR_SF (1<<3) | 1407 | # define IR_SF (1<<3) |
| 1408 | #define IR_SIR (1<<4) | 1408 | # define IR_SIR (1<<4) |
| 1409 | #define IR_MIR (1<<5) | 1409 | # define IR_MIR (1<<5) |
| 1410 | #define IR_FIR (1<<6) | 1410 | # define IR_FIR (1<<6) |
| 1411 | #define IR_16CRC (1<<7) | 1411 | # define IR_16CRC (1<<7) |
| 1412 | #define IR_TD (1<<8) | 1412 | # define IR_TD (1<<8) |
| 1413 | #define IR_RX_ALL (1<<9) | 1413 | # define IR_RX_ALL (1<<9) |
| 1414 | #define IR_DMA_ENABLE (1<<10) | 1414 | # define IR_DMA_ENABLE (1<<10) |
| 1415 | #define IR_RX_ENABLE (1<<11) | 1415 | # define IR_RX_ENABLE (1<<11) |
| 1416 | #define IR_TX_ENABLE (1<<12) | 1416 | # define IR_TX_ENABLE (1<<12) |
| 1417 | #define IR_LOOPBACK (1<<14) | 1417 | # define IR_LOOPBACK (1<<14) |
| 1418 | #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ | 1418 | # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ |
| 1419 | IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) | 1419 | IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) |
| 1420 | #define IR_SIR_FLAGS (IRDA_BASE+0x24) | 1420 | #define IR_SIR_FLAGS (IRDA_BASE+0x24) |
| 1421 | #define IR_ENABLE (IRDA_BASE+0x28) | 1421 | #define IR_ENABLE (IRDA_BASE+0x28) |
| 1422 | #define IR_RX_STATUS (1<<9) | 1422 | # define IR_RX_STATUS (1<<9) |
| 1423 | #define IR_TX_STATUS (1<<10) | 1423 | # define IR_TX_STATUS (1<<10) |
| 1424 | #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) | 1424 | #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) |
| 1425 | #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) | 1425 | #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) |
| 1426 | #define IR_MAX_PKT_LEN (IRDA_BASE+0x34) | 1426 | #define IR_MAX_PKT_LEN (IRDA_BASE+0x34) |
| 1427 | #define IR_RX_BYTE_CNT (IRDA_BASE+0x38) | 1427 | #define IR_RX_BYTE_CNT (IRDA_BASE+0x38) |
| 1428 | #define IR_CONFIG_2 (IRDA_BASE+0x3C) | 1428 | #define IR_CONFIG_2 (IRDA_BASE+0x3C) |
| 1429 | #define IR_MODE_INV (1<<0) | 1429 | # define IR_MODE_INV (1<<0) |
| 1430 | #define IR_ONE_PIN (1<<1) | 1430 | # define IR_ONE_PIN (1<<1) |
| 1431 | #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) | 1431 | #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) |
| 1432 | 1432 | ||
| 1433 | /* GPIO */ | 1433 | /* GPIO */ |
| 1434 | #define SYS_PINFUNC 0xB190002C | 1434 | #define SYS_PINFUNC 0xB190002C |
| 1435 | #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ | 1435 | # define SYS_PF_USB (1<<15) /* 2nd USB device/host */ |
| 1436 | #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ | 1436 | # define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ |
| 1437 | #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ | 1437 | # define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ |
| 1438 | #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ | 1438 | # define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ |
| 1439 | #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ | 1439 | # define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ |
| 1440 | #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ | 1440 | # define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ |
| 1441 | #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ | 1441 | # define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ |
| 1442 | #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ | 1442 | # define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ |
| 1443 | #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ | 1443 | # define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ |
| 1444 | #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ | 1444 | # define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ |
| 1445 | #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ | 1445 | # define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ |
| 1446 | #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ | 1446 | # define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ |
| 1447 | #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ | 1447 | # define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ |
| 1448 | #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ | 1448 | # define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ |
| 1449 | #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ | 1449 | # define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ |
| 1450 | #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ | 1450 | # define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ |
| 1451 | 1451 | ||
| 1452 | /* Au1100 Only */ | 1452 | /* Au1100 Only */ |
| 1453 | #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ | 1453 | # define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ |
| 1454 | #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ | 1454 | # define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ |
| 1455 | #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ | 1455 | # define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ |
| 1456 | #define SYS_PF_EX0 (1<<9) /* gpio2/clock */ | 1456 | # define SYS_PF_EX0 (1<<9) /* gpio2/clock */ |
| 1457 | 1457 | ||
| 1458 | /* Au1550 Only. Redefines lots of pins */ | 1458 | /* Au1550 Only. Redefines lots of pins */ |
| 1459 | #define SYS_PF_PSC2_MASK (7 << 17) | 1459 | # define SYS_PF_PSC2_MASK (7 << 17) |
| 1460 | #define SYS_PF_PSC2_AC97 (0) | 1460 | # define SYS_PF_PSC2_AC97 (0) |
| 1461 | #define SYS_PF_PSC2_SPI (0) | 1461 | # define SYS_PF_PSC2_SPI (0) |
| 1462 | #define SYS_PF_PSC2_I2S (1 << 17) | 1462 | # define SYS_PF_PSC2_I2S (1 << 17) |
| 1463 | #define SYS_PF_PSC2_SMBUS (3 << 17) | 1463 | # define SYS_PF_PSC2_SMBUS (3 << 17) |
| 1464 | #define SYS_PF_PSC2_GPIO (7 << 17) | 1464 | # define SYS_PF_PSC2_GPIO (7 << 17) |
| 1465 | #define SYS_PF_PSC3_MASK (7 << 20) | 1465 | # define SYS_PF_PSC3_MASK (7 << 20) |
| 1466 | #define SYS_PF_PSC3_AC97 (0) | 1466 | # define SYS_PF_PSC3_AC97 (0) |
| 1467 | #define SYS_PF_PSC3_SPI (0) | 1467 | # define SYS_PF_PSC3_SPI (0) |
| 1468 | #define SYS_PF_PSC3_I2S (1 << 20) | 1468 | # define SYS_PF_PSC3_I2S (1 << 20) |
| 1469 | #define SYS_PF_PSC3_SMBUS (3 << 20) | 1469 | # define SYS_PF_PSC3_SMBUS (3 << 20) |
| 1470 | #define SYS_PF_PSC3_GPIO (7 << 20) | 1470 | # define SYS_PF_PSC3_GPIO (7 << 20) |
| 1471 | #define SYS_PF_PSC1_S1 (1 << 1) | 1471 | # define SYS_PF_PSC1_S1 (1 << 1) |
| 1472 | #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) | 1472 | # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) |
| 1473 | 1473 | ||
| 1474 | /* Au1200 Only */ | 1474 | /* Au1200 Only */ |
| 1475 | #ifdef CONFIG_SOC_AU1200 | 1475 | #ifdef CONFIG_SOC_AU1200 |
| @@ -1530,104 +1530,104 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; | |||
| 1530 | 1530 | ||
| 1531 | /* Clock Controller */ | 1531 | /* Clock Controller */ |
| 1532 | #define SYS_FREQCTRL0 0xB1900020 | 1532 | #define SYS_FREQCTRL0 0xB1900020 |
| 1533 | #define SYS_FC_FRDIV2_BIT 22 | 1533 | # define SYS_FC_FRDIV2_BIT 22 |
| 1534 | #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) | 1534 | # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) |
| 1535 | #define SYS_FC_FE2 (1<<21) | 1535 | # define SYS_FC_FE2 (1<<21) |
| 1536 | #define SYS_FC_FS2 (1<<20) | 1536 | # define SYS_FC_FS2 (1<<20) |
| 1537 | #define SYS_FC_FRDIV1_BIT 12 | 1537 | # define SYS_FC_FRDIV1_BIT 12 |
| 1538 | #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) | 1538 | # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) |
| 1539 | #define SYS_FC_FE1 (1<<11) | 1539 | # define SYS_FC_FE1 (1<<11) |
| 1540 | #define SYS_FC_FS1 (1<<10) | 1540 | # define SYS_FC_FS1 (1<<10) |
| 1541 | #define SYS_FC_FRDIV0_BIT 2 | 1541 | # define SYS_FC_FRDIV0_BIT 2 |
| 1542 | #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) | 1542 | # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) |
| 1543 | #define SYS_FC_FE0 (1<<1) | 1543 | # define SYS_FC_FE0 (1<<1) |
| 1544 | #define SYS_FC_FS0 (1<<0) | 1544 | # define SYS_FC_FS0 (1<<0) |
| 1545 | #define SYS_FREQCTRL1 0xB1900024 | 1545 | #define SYS_FREQCTRL1 0xB1900024 |
| 1546 | #define SYS_FC_FRDIV5_BIT 22 | 1546 | # define SYS_FC_FRDIV5_BIT 22 |
| 1547 | #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) | 1547 | # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) |
| 1548 | #define SYS_FC_FE5 (1<<21) | 1548 | # define SYS_FC_FE5 (1<<21) |
| 1549 | #define SYS_FC_FS5 (1<<20) | 1549 | # define SYS_FC_FS5 (1<<20) |
| 1550 | #define SYS_FC_FRDIV4_BIT 12 | 1550 | # define SYS_FC_FRDIV4_BIT 12 |
| 1551 | #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) | 1551 | # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) |
| 1552 | #define SYS_FC_FE4 (1<<11) | 1552 | # define SYS_FC_FE4 (1<<11) |
| 1553 | #define SYS_FC_FS4 (1<<10) | 1553 | # define SYS_FC_FS4 (1<<10) |
| 1554 | #define SYS_FC_FRDIV3_BIT 2 | 1554 | # define SYS_FC_FRDIV3_BIT 2 |
| 1555 | #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) | 1555 | # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) |
| 1556 | #define SYS_FC_FE3 (1<<1) | 1556 | # define SYS_FC_FE3 (1<<1) |
| 1557 | #define SYS_FC_FS3 (1<<0) | 1557 | # define SYS_FC_FS3 (1<<0) |
| 1558 | #define SYS_CLKSRC 0xB1900028 | 1558 | #define SYS_CLKSRC 0xB1900028 |
| 1559 | #define SYS_CS_ME1_BIT 27 | 1559 | # define SYS_CS_ME1_BIT 27 |
| 1560 | #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) | 1560 | # define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) |
| 1561 | #define SYS_CS_DE1 (1<<26) | 1561 | # define SYS_CS_DE1 (1<<26) |
| 1562 | #define SYS_CS_CE1 (1<<25) | 1562 | # define SYS_CS_CE1 (1<<25) |
| 1563 | #define SYS_CS_ME0_BIT 22 | 1563 | # define SYS_CS_ME0_BIT 22 |
| 1564 | #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) | 1564 | # define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) |
| 1565 | #define SYS_CS_DE0 (1<<21) | 1565 | # define SYS_CS_DE0 (1<<21) |
| 1566 | #define SYS_CS_CE0 (1<<20) | 1566 | # define SYS_CS_CE0 (1<<20) |
| 1567 | #define SYS_CS_MI2_BIT 17 | 1567 | # define SYS_CS_MI2_BIT 17 |
| 1568 | #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) | 1568 | # define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) |
| 1569 | #define SYS_CS_DI2 (1<<16) | 1569 | # define SYS_CS_DI2 (1<<16) |
| 1570 | #define SYS_CS_CI2 (1<<15) | 1570 | # define SYS_CS_CI2 (1<<15) |
| 1571 | #ifdef CONFIG_SOC_AU1100 | 1571 | #ifdef CONFIG_SOC_AU1100 |
| 1572 | #define SYS_CS_ML_BIT 7 | 1572 | # define SYS_CS_ML_BIT 7 |
| 1573 | #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) | 1573 | # define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) |
| 1574 | #define SYS_CS_DL (1<<6) | 1574 | # define SYS_CS_DL (1<<6) |
| 1575 | #define SYS_CS_CL (1<<5) | 1575 | # define SYS_CS_CL (1<<5) |
| 1576 | #else | 1576 | #else |
| 1577 | #define SYS_CS_MUH_BIT 12 | 1577 | # define SYS_CS_MUH_BIT 12 |
| 1578 | #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) | 1578 | # define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) |
| 1579 | #define SYS_CS_DUH (1<<11) | 1579 | # define SYS_CS_DUH (1<<11) |
| 1580 | #define SYS_CS_CUH (1<<10) | 1580 | # define SYS_CS_CUH (1<<10) |
| 1581 | #define SYS_CS_MUD_BIT 7 | 1581 | # define SYS_CS_MUD_BIT 7 |
| 1582 | #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) | 1582 | # define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) |
| 1583 | #define SYS_CS_DUD (1<<6) | 1583 | # define SYS_CS_DUD (1<<6) |
| 1584 | #define SYS_CS_CUD (1<<5) | 1584 | # define SYS_CS_CUD (1<<5) |
| 1585 | #endif | 1585 | #endif |
| 1586 | #define SYS_CS_MIR_BIT 2 | 1586 | # define SYS_CS_MIR_BIT 2 |
| 1587 | #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) | 1587 | # define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) |
| 1588 | #define SYS_CS_DIR (1<<1) | 1588 | # define SYS_CS_DIR (1<<1) |
| 1589 | #define SYS_CS_CIR (1<<0) | 1589 | # define SYS_CS_CIR (1<<0) |
| 1590 | 1590 | ||
| 1591 | #define SYS_CS_MUX_AUX 0x1 | 1591 | # define SYS_CS_MUX_AUX 0x1 |
| 1592 | #define SYS_CS_MUX_FQ0 0x2 | 1592 | # define SYS_CS_MUX_FQ0 0x2 |
| 1593 | #define SYS_CS_MUX_FQ1 0x3 | 1593 | # define SYS_CS_MUX_FQ1 0x3 |
| 1594 | #define SYS_CS_MUX_FQ2 0x4 | 1594 | # define SYS_CS_MUX_FQ2 0x4 |
| 1595 | #define SYS_CS_MUX_FQ3 0x5 | 1595 | # define SYS_CS_MUX_FQ3 0x5 |
| 1596 | #define SYS_CS_MUX_FQ4 0x6 | 1596 | # define SYS_CS_MUX_FQ4 0x6 |
| 1597 | #define SYS_CS_MUX_FQ5 0x7 | 1597 | # define SYS_CS_MUX_FQ5 0x7 |
| 1598 | #define SYS_CPUPLL 0xB1900060 | 1598 | #define SYS_CPUPLL 0xB1900060 |
| 1599 | #define SYS_AUXPLL 0xB1900064 | 1599 | #define SYS_AUXPLL 0xB1900064 |
| 1600 | 1600 | ||
| 1601 | /* AC97 Controller */ | 1601 | /* AC97 Controller */ |
| 1602 | #define AC97C_CONFIG 0xB0000000 | 1602 | #define AC97C_CONFIG 0xB0000000 |
| 1603 | #define AC97C_RECV_SLOTS_BIT 13 | 1603 | # define AC97C_RECV_SLOTS_BIT 13 |
| 1604 | #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) | 1604 | # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) |
| 1605 | #define AC97C_XMIT_SLOTS_BIT 3 | 1605 | # define AC97C_XMIT_SLOTS_BIT 3 |
| 1606 | #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) | 1606 | # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) |
| 1607 | #define AC97C_SG (1<<2) | 1607 | # define AC97C_SG (1<<2) |
| 1608 | #define AC97C_SYNC (1<<1) | 1608 | # define AC97C_SYNC (1<<1) |
| 1609 | #define AC97C_RESET (1<<0) | 1609 | # define AC97C_RESET (1<<0) |
| 1610 | #define AC97C_STATUS 0xB0000004 | 1610 | #define AC97C_STATUS 0xB0000004 |
| 1611 | #define AC97C_XU (1<<11) | 1611 | # define AC97C_XU (1<<11) |
| 1612 | #define AC97C_XO (1<<10) | 1612 | # define AC97C_XO (1<<10) |
| 1613 | #define AC97C_RU (1<<9) | 1613 | # define AC97C_RU (1<<9) |
| 1614 | #define AC97C_RO (1<<8) | 1614 | # define AC97C_RO (1<<8) |
| 1615 | #define AC97C_READY (1<<7) | 1615 | # define AC97C_READY (1<<7) |
| 1616 | #define AC97C_CP (1<<6) | 1616 | # define AC97C_CP (1<<6) |
| 1617 | #define AC97C_TR (1<<5) | 1617 | # define AC97C_TR (1<<5) |
| 1618 | #define AC97C_TE (1<<4) | 1618 | # define AC97C_TE (1<<4) |
| 1619 | #define AC97C_TF (1<<3) | 1619 | # define AC97C_TF (1<<3) |
| 1620 | #define AC97C_RR (1<<2) | 1620 | # define AC97C_RR (1<<2) |
| 1621 | #define AC97C_RE (1<<1) | 1621 | # define AC97C_RE (1<<1) |
| 1622 | #define AC97C_RF (1<<0) | 1622 | # define AC97C_RF (1<<0) |
| 1623 | #define AC97C_DATA 0xB0000008 | 1623 | #define AC97C_DATA 0xB0000008 |
| 1624 | #define AC97C_CMD 0xB000000C | 1624 | #define AC97C_CMD 0xB000000C |
| 1625 | #define AC97C_WD_BIT 16 | 1625 | # define AC97C_WD_BIT 16 |
| 1626 | #define AC97C_READ (1<<7) | 1626 | # define AC97C_READ (1<<7) |
| 1627 | #define AC97C_INDEX_MASK 0x7f | 1627 | # define AC97C_INDEX_MASK 0x7f |
| 1628 | #define AC97C_CNTRL 0xB0000010 | 1628 | #define AC97C_CNTRL 0xB0000010 |
| 1629 | #define AC97C_RS (1<<1) | 1629 | # define AC97C_RS (1<<1) |
| 1630 | #define AC97C_CE (1<<0) | 1630 | # define AC97C_CE (1<<0) |
| 1631 | 1631 | ||
| 1632 | 1632 | ||
| 1633 | /* Secure Digital (SD) Controller */ | 1633 | /* Secure Digital (SD) Controller */ |
| @@ -1636,12 +1636,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; | |||
| 1636 | #define SD1_XMIT_FIFO 0xB0680000 | 1636 | #define SD1_XMIT_FIFO 0xB0680000 |
| 1637 | #define SD1_RECV_FIFO 0xB0680004 | 1637 | #define SD1_RECV_FIFO 0xB0680004 |
| 1638 | 1638 | ||
| 1639 | #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) | 1639 | #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) |
| 1640 | /* Au1500 PCI Controller */ | 1640 | /* Au1500 PCI Controller */ |
| 1641 | #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr | 1641 | #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr |
| 1642 | #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) | 1642 | #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) |
| 1643 | #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) | 1643 | #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) |
| 1644 | #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) | 1644 | # define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) |
| 1645 | #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) | 1645 | #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) |
| 1646 | #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) | 1646 | #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) |
| 1647 | #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) | 1647 | #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) |