diff options
Diffstat (limited to 'include/asm-mips/it8172/it8172_pci.h')
| -rw-r--r-- | include/asm-mips/it8172/it8172_pci.h | 108 |
1 files changed, 0 insertions, 108 deletions
diff --git a/include/asm-mips/it8172/it8172_pci.h b/include/asm-mips/it8172/it8172_pci.h deleted file mode 100644 index 42c61f56eeba..000000000000 --- a/include/asm-mips/it8172/it8172_pci.h +++ /dev/null | |||
| @@ -1,108 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * BRIEF MODULE DESCRIPTION | ||
| 4 | * IT8172 system controller specific pci defines. | ||
| 5 | * | ||
| 6 | * Copyright 2000 MontaVista Software Inc. | ||
| 7 | * Author: MontaVista Software, Inc. | ||
| 8 | * ppopov@mvista.com or source@mvista.com | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 21 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 22 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License along | ||
| 27 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 28 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _8172PCI_H_ | ||
| 32 | #define _8172PCI_H_ | ||
| 33 | |||
| 34 | // PCI configuration space Type0 | ||
| 35 | #define PCI_IDREG 0x00 | ||
| 36 | #define PCI_CMDSTSREG 0x04 | ||
| 37 | #define PCI_CLASSREG 0x08 | ||
| 38 | #define PCI_BHLCREG 0x0C | ||
| 39 | #define PCI_BASE1REG 0x10 | ||
| 40 | #define PCI_BASE2REG 0x14 | ||
| 41 | #define PCI_BASE3REG 0x18 | ||
| 42 | #define PCI_BASE4REG 0x1C | ||
| 43 | #define PCI_BASE5REG 0x20 | ||
| 44 | #define PCI_BASE6REG 0x24 | ||
| 45 | #define PCI_ROMBASEREG 0x30 | ||
| 46 | #define PCI_INTRREG 0x3C | ||
| 47 | |||
| 48 | // PCI configuration space Type1 | ||
| 49 | #define PCI_BUSNOREG 0x18 | ||
| 50 | |||
| 51 | #define IT_PCI_VENDORID(x) ((x) & 0xFFFF) | ||
| 52 | #define IT_PCI_DEVICEID(x) (((x)>>16) & 0xFFFF) | ||
| 53 | |||
| 54 | // Command register | ||
| 55 | #define PCI_CMD_IOEN 0x00000001 | ||
| 56 | #define PCI_CMD_MEMEN 0x00000002 | ||
| 57 | #define PCI_CMD_BUSMASTER 0x00000004 | ||
| 58 | #define PCI_CMD_SPCYCLE 0x00000008 | ||
| 59 | #define PCI_CMD_WRINV 0x00000010 | ||
| 60 | #define PCI_CMD_VGASNOOP 0x00000020 | ||
| 61 | #define PCI_CMD_PERR 0x00000040 | ||
| 62 | #define PCI_CMD_WAITCTRL 0x00000080 | ||
| 63 | #define PCI_CMD_SERR 0x00000100 | ||
| 64 | #define PCI_CMD_FAST_BACKTOBACK 0x00000200 | ||
| 65 | |||
| 66 | // Status register | ||
| 67 | #define PCI_STS_66MHZ 0x00200000 | ||
| 68 | #define PCI_STS_SUPPORT_UDF 0x00400000 | ||
| 69 | #define PCI_STS_FAST_BACKTOBACK 0x00800000 | ||
| 70 | #define PCI_STS_DATA_PERR 0x01000000 | ||
| 71 | #define PCI_STS_DEVSEL0 0x02000000 | ||
| 72 | #define PCI_STS_DEVSEL1 0x04000000 | ||
| 73 | #define PCI_STS_SIG_TGTABORT 0x08000000 | ||
| 74 | #define PCI_STS_RCV_TGTABORT 0x10000000 | ||
| 75 | #define PCI_STS_RCV_MSTABORT 0x20000000 | ||
| 76 | #define PCI_STS_SYSERR 0x40000000 | ||
| 77 | #define PCI_STS_DETCT_PERR 0x80000000 | ||
| 78 | |||
| 79 | #define IT_PCI_CLASS(x) (((x)>>24) & 0xFF) | ||
| 80 | #define IT_PCI_SUBCLASS(x) (((x)>>16) & 0xFF) | ||
| 81 | #define IT_PCI_INTERFACE(x) (((x)>>8) & 0xFF) | ||
| 82 | #define IT_PCI_REVISION(x) ((x) & 0xFF) | ||
| 83 | |||
| 84 | // PCI class code | ||
| 85 | #define PCI_CLASS_BRIDGE 0x06 | ||
| 86 | |||
| 87 | // bridge subclass | ||
| 88 | #define PCI_SUBCLASS_BRIDGE_HOST 0x00 | ||
| 89 | #define PCI_SUBCLASS_BRIDGE_PCI 0x04 | ||
| 90 | |||
| 91 | // BHLCREG | ||
| 92 | #define IT_PCI_BIST(x) (((x)>>24) & 0xFF) | ||
| 93 | #define IT_PCI_HEADERTYPE(x) (((x)>>16) & 0xFF) | ||
| 94 | #define IT_PCI_LATENCYTIMER(x) (((x)>>8) & 0xFF) | ||
| 95 | #define IT_PCI_CACHELINESIZE(x) ((x) & 0xFF) | ||
| 96 | |||
| 97 | #define PCI_MULTIFUNC 0x80 | ||
| 98 | |||
| 99 | // INTRREG | ||
| 100 | #define IT_PCI_MAXLAT(x) (((x)>>24) & 0xFF) | ||
| 101 | #define IT_PCI_MINGNT(x) (((x)>>16) & 0xFF) | ||
| 102 | #define IT_PCI_INTRPIN(x) (((x)>>8) & 0xFF) | ||
| 103 | #define IT_PCI_INTRLINE(x) ((x) & 0xFF) | ||
| 104 | |||
| 105 | #define PCI_VENDOR_NEC 0x1033 | ||
| 106 | #define PCI_VENDOR_DEC 0x1101 | ||
| 107 | |||
| 108 | #endif // _8172PCI_H_ | ||