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-rw-r--r--include/asm-mips/it8172/it8172_int.h144
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diff --git a/include/asm-mips/it8172/it8172_int.h b/include/asm-mips/it8172/it8172_int.h
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1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * ITE 8172 Interrupt Numbering
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#ifndef _MIPS_ITEINT_H
32#define _MIPS_ITEINT_H
33
34/*
35 * Here's the "strategy":
36 * We number the LPC serial irqs from 0 to 15,
37 * the local bus irqs from 16 to 31,
38 * the pci dev register interrupts from 32 to 47,
39 * and the non-maskable ints from 48 to 53.
40 */
41
42#define IT8172_LPC_IRQ_BASE 0 /* first LPC int number */
43#define IT8172_SERIRQ_0 (IT8172_LPC_IRQ_BASE + 0)
44#define IT8172_SERIRQ_1 (IT8172_LPC_IRQ_BASE + 1)
45#define IT8172_SERIRQ_2 (IT8172_LPC_IRQ_BASE + 2)
46#define IT8172_SERIRQ_3 (IT8172_LPC_IRQ_BASE + 3)
47#define IT8172_SERIRQ_4 (IT8172_LPC_IRQ_BASE + 4)
48#define IT8172_SERIRQ_5 (IT8172_LPC_IRQ_BASE + 5)
49#define IT8172_SERIRQ_6 (IT8172_LPC_IRQ_BASE + 6)
50#define IT8172_SERIRQ_7 (IT8172_LPC_IRQ_BASE + 7)
51#define IT8172_SERIRQ_8 (IT8172_LPC_IRQ_BASE + 8)
52#define IT8172_SERIRQ_9 (IT8172_LPC_IRQ_BASE + 9)
53#define IT8172_SERIRQ_10 (IT8172_LPC_IRQ_BASE + 10)
54#define IT8172_SERIRQ_11 (IT8172_LPC_IRQ_BASE + 11)
55#define IT8172_SERIRQ_12 (IT8172_LPC_IRQ_BASE + 12)
56#define IT8172_SERIRQ_13 (IT8172_LPC_IRQ_BASE + 13)
57#define IT8172_SERIRQ_14 (IT8172_LPC_IRQ_BASE + 14)
58#define IT8172_SERIRQ_15 (IT8172_LPC_IRQ_BASE + 15)
59
60#define IT8172_LB_IRQ_BASE 16 /* first local bus int number */
61#define IT8172_PPR_IRQ (IT8172_LB_IRQ_BASE + 0) /* parallel port */
62#define IT8172_TIMER0_IRQ (IT8172_LB_IRQ_BASE + 1)
63#define IT8172_TIMER1_IRQ (IT8172_LB_IRQ_BASE + 2)
64#define IT8172_I2C_IRQ (IT8172_LB_IRQ_BASE + 3)
65#define IT8172_GPIO_IRQ (IT8172_LB_IRQ_BASE + 4)
66#define IT8172_CIR0_IRQ (IT8172_LB_IRQ_BASE + 5)
67#define IT8172_CIR1_IRQ (IT8172_LB_IRQ_BASE + 6)
68#define IT8172_UART_IRQ (IT8172_LB_IRQ_BASE + 7)
69#define IT8172_SCR0_IRQ (IT8172_LB_IRQ_BASE + 8)
70#define IT8172_SCR1_IRQ (IT8172_LB_IRQ_BASE + 9)
71#define IT8172_RTC_IRQ (IT8172_LB_IRQ_BASE + 10)
72#define IT8172_IOCHK_IRQ (IT8172_LB_IRQ_BASE + 11)
73/* 12 - 15 reserved */
74
75/*
76 * Note here that the pci dev registers includes bits for more than
77 * just the pci devices.
78 */
79#define IT8172_PCI_DEV_IRQ_BASE 32 /* first pci dev irq */
80#define IT8172_AC97_IRQ (IT8172_PCI_DEV_IRQ_BASE + 0)
81#define IT8172_MC68K_IRQ (IT8172_PCI_DEV_IRQ_BASE + 1)
82#define IT8172_IDE_IRQ (IT8172_PCI_DEV_IRQ_BASE + 2)
83#define IT8172_USB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 3)
84#define IT8172_BRIDGE_MASTER_IRQ (IT8172_PCI_DEV_IRQ_BASE + 4)
85#define IT8172_BRIDGE_TARGET_IRQ (IT8172_PCI_DEV_IRQ_BASE + 5)
86#define IT8172_PCI_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 6)
87#define IT8172_PCI_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 7)
88#define IT8172_PCI_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 8)
89#define IT8172_PCI_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 9)
90#define IT8172_S_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 10)
91#define IT8172_S_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 11)
92#define IT8172_S_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 12)
93#define IT8172_S_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 13)
94#define IT8172_CDMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 14)
95#define IT8172_DMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 15)
96
97#define IT8172_NMI_IRQ_BASE 48
98#define IT8172_SER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 0)
99#define IT8172_PCI_NMI_IRQ (IT8172_NMI_IRQ_BASE + 1)
100#define IT8172_RTC_NMI_IRQ (IT8172_NMI_IRQ_BASE + 2)
101#define IT8172_CPUIF_NMI_IRQ (IT8172_NMI_IRQ_BASE + 3)
102#define IT8172_PMER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 4)
103#define IT8172_POWER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 5)
104
105#define IT8172_LAST_IRQ (IT8172_POWER_NMI_IRQ)
106/* Finally, let's move over here the mips cpu timer interrupt.
107 */
108#define MIPS_CPU_TIMER_IRQ (NR_IRQS-1)
109
110/*
111 * IT8172 Interrupt Controller Registers
112 */
113struct it8172_intc_regs {
114 volatile unsigned short lb_req; /* offset 0 */
115 volatile unsigned short lb_mask;
116 volatile unsigned short lb_trigger;
117 volatile unsigned short lb_level;
118 unsigned char pad0[8];
119
120 volatile unsigned short lpc_req; /* offset 0x10 */
121 volatile unsigned short lpc_mask;
122 volatile unsigned short lpc_trigger;
123 volatile unsigned short lpc_level;
124 unsigned char pad1[8];
125
126 volatile unsigned short pci_req; /* offset 0x20 */
127 volatile unsigned short pci_mask;
128 volatile unsigned short pci_trigger;
129 volatile unsigned short pci_level;
130 unsigned char pad2[8];
131
132 volatile unsigned short nmi_req; /* offset 0x30 */
133 volatile unsigned short nmi_mask;
134 volatile unsigned short nmi_trigger;
135 volatile unsigned short nmi_level;
136 unsigned char pad3[6];
137
138 volatile unsigned short nmi_redir; /* offset 0x3E */
139 unsigned char pad4[0xBE];
140
141 volatile unsigned short intstatus; /* offset 0xFE */
142};
143
144#endif /* _MIPS_ITEINT_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 22:47:35 -0500