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-rw-r--r--include/asm-mips/irq.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 91803ba30ff2..97102ebc54b1 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -24,7 +24,7 @@ static inline int irq_canonicalize(int irq)
24#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ 24#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
25#endif 25#endif
26 26
27#ifdef CONFIG_MIPS_MT_SMTC 27#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
28/* 28/*
29 * Clear interrupt mask handling "backstop" if irq_hwmask 29 * Clear interrupt mask handling "backstop" if irq_hwmask
30 * entry so indicates. This implies that the ack() or end() 30 * entry so indicates. This implies that the ack() or end()
@@ -72,4 +72,13 @@ extern int allocate_irqno(void);
72extern void alloc_legacy_irqno(void); 72extern void alloc_legacy_irqno(void);
73extern void free_irqno(unsigned int irq); 73extern void free_irqno(unsigned int irq);
74 74
75/*
76 * Before R2 the timer and performance counter interrupts were both fixed to
77 * IE7. Since R2 their number has to be read from the c0_intctl register.
78 */
79#define CP0_LEGACY_COMPARE_IRQ 7
80
81extern int cp0_compare_irq;
82extern int cp0_perfcount_irq;
83
75#endif /* _ASM_IRQ_H */ 84#endif /* _ASM_IRQ_H */