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-rw-r--r--include/asm-mips/ip32/crime.h161
-rw-r--r--include/asm-mips/ip32/ip32_ints.h94
-rw-r--r--include/asm-mips/ip32/mace.h334
-rw-r--r--include/asm-mips/ip32/machine.h21
4 files changed, 610 insertions, 0 deletions
diff --git a/include/asm-mips/ip32/crime.h b/include/asm-mips/ip32/crime.h
new file mode 100644
index 000000000000..152879bae20f
--- /dev/null
+++ b/include/asm-mips/ip32/crime.h
@@ -0,0 +1,161 @@
1/*
2 * Definitions for the SGI CRIME (CPU, Rendering, Interconnect and Memory
3 * Engine)
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 2000 Harald Koerfgen
10 */
11
12#ifndef __ASM_CRIME_H__
13#define __ASM_CRIME_H__
14
15/*
16 * Address map
17 */
18#define CRIME_BASE 0x14000000 /* physical */
19
20#undef BIT
21#define BIT(x) (1UL << (x))
22
23struct sgi_crime {
24 volatile unsigned long id;
25#define CRIME_ID_MASK 0xff
26#define CRIME_ID_IDBITS 0xf0
27#define CRIME_ID_IDVALUE 0xa0
28#define CRIME_ID_REV 0x0f
29#define CRIME_REV_PETTY 0x00
30#define CRIME_REV_11 0x11
31#define CRIME_REV_13 0x13
32#define CRIME_REV_14 0x14
33
34 volatile unsigned long control;
35#define CRIME_CONTROL_MASK 0x3fff
36#define CRIME_CONTROL_TRITON_SYSADC 0x2000
37#define CRIME_CONTROL_CRIME_SYSADC 0x1000
38#define CRIME_CONTROL_HARD_RESET 0x0800
39#define CRIME_CONTROL_SOFT_RESET 0x0400
40#define CRIME_CONTROL_DOG_ENA 0x0200
41#define CRIME_CONTROL_ENDIANESS 0x0100
42#define CRIME_CONTROL_ENDIAN_BIG 0x0100
43#define CRIME_CONTROL_ENDIAN_LITTLE 0x0000
44#define CRIME_CONTROL_CQUEUE_HWM 0x000f
45#define CRIME_CONTROL_CQUEUE_SHFT 0
46#define CRIME_CONTROL_WBUF_HWM 0x00f0
47#define CRIME_CONTROL_WBUF_SHFT 8
48
49 volatile unsigned long istat;
50 volatile unsigned long imask;
51 volatile unsigned long soft_int;
52 volatile unsigned long hard_int;
53#define MACE_VID_IN1_INT BIT(0)
54#define MACE_VID_IN2_INT BIT(1)
55#define MACE_VID_OUT_INT BIT(2)
56#define MACE_ETHERNET_INT BIT(3)
57#define MACE_SUPERIO_INT BIT(4)
58#define MACE_MISC_INT BIT(5)
59#define MACE_AUDIO_INT BIT(6)
60#define MACE_PCI_BRIDGE_INT BIT(7)
61#define MACEPCI_SCSI0_INT BIT(8)
62#define MACEPCI_SCSI1_INT BIT(9)
63#define MACEPCI_SLOT0_INT BIT(10)
64#define MACEPCI_SLOT1_INT BIT(11)
65#define MACEPCI_SLOT2_INT BIT(12)
66#define MACEPCI_SHARED0_INT BIT(13)
67#define MACEPCI_SHARED1_INT BIT(14)
68#define MACEPCI_SHARED2_INT BIT(15)
69#define CRIME_GBE0_INT BIT(16)
70#define CRIME_GBE1_INT BIT(17)
71#define CRIME_GBE2_INT BIT(18)
72#define CRIME_GBE3_INT BIT(19)
73#define CRIME_CPUERR_INT BIT(20)
74#define CRIME_MEMERR_INT BIT(21)
75#define CRIME_RE_EMPTY_E_INT BIT(22)
76#define CRIME_RE_FULL_E_INT BIT(23)
77#define CRIME_RE_IDLE_E_INT BIT(24)
78#define CRIME_RE_EMPTY_L_INT BIT(25)
79#define CRIME_RE_FULL_L_INT BIT(26)
80#define CRIME_RE_IDLE_L_INT BIT(27)
81#define CRIME_SOFT0_INT BIT(28)
82#define CRIME_SOFT1_INT BIT(29)
83#define CRIME_SOFT2_INT BIT(30)
84#define CRIME_SYSCORERR_INT CRIME_SOFT2_INT
85#define CRIME_VICE_INT BIT(31)
86/* Masks for deciding who handles the interrupt */
87#define CRIME_MACE_INT_MASK 0x8f
88#define CRIME_MACEISA_INT_MASK 0x70
89#define CRIME_MACEPCI_INT_MASK 0xff00
90#define CRIME_CRIME_INT_MASK 0xffff0000
91
92 volatile unsigned long watchdog;
93#define CRIME_DOG_POWER_ON_RESET 0x00010000
94#define CRIME_DOG_WARM_RESET 0x00080000
95#define CRIME_DOG_TIMEOUT (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
96#define CRIME_DOG_VALUE 0x00007fff
97
98 volatile unsigned long timer;
99#define CRIME_MASTER_FREQ 66666500 /* Crime upcounter frequency */
100#define CRIME_NS_PER_TICK 15 /* for delay_calibrate */
101
102 volatile unsigned long cpu_error_addr;
103#define CRIME_CPU_ERROR_ADDR_MASK 0x3ffffffff
104
105 volatile unsigned long cpu_error_stat;
106#define CRIME_CPU_ERROR_MASK 0x7 /* cpu error stat is 3 bits */
107#define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4
108#define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2
109#define CRIME_CPU_ERROR_CPU_WRT_PRTY 0x1
110
111 unsigned long _pad0[54];
112
113 volatile unsigned long mc_ctrl;
114 volatile unsigned long bank_ctrl[8];
115#define CRIME_MEM_BANK_CONTROL_MASK 0x11f /* 9 bits 7:5 reserved */
116#define CRIME_MEM_BANK_CONTROL_ADDR 0x01f
117#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100
118#define CRIME_MAXBANKS 8
119
120 volatile unsigned long mem_ref_counter;
121#define CRIME_MEM_REF_COUNTER_MASK 0x3ff /* 10bit */
122
123 volatile unsigned long mem_error_stat;
124#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */
125#define CRIME_MEM_ERROR_MACE_ID 0x0000007f
126#define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080
127#define CRIME_MEM_ERROR_RE_ID 0x00007f00
128#define CRIME_MEM_ERROR_RE_ACCESS 0x00008000
129#define CRIME_MEM_ERROR_GBE_ACCESS 0x00010000
130#define CRIME_MEM_ERROR_VICE_ACCESS 0x00020000
131#define CRIME_MEM_ERROR_CPU_ACCESS 0x00040000
132#define CRIME_MEM_ERROR_RESERVED 0x00080000
133#define CRIME_MEM_ERROR_SOFT_ERR 0x00100000
134#define CRIME_MEM_ERROR_HARD_ERR 0x00200000
135#define CRIME_MEM_ERROR_MULTIPLE 0x00400000
136#define CRIME_MEM_ERROR_ECC 0x01800000
137#define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000
138#define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000
139#define CRIME_MEM_ERROR_INV 0x0e000000
140#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
141#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000
142#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
143
144 volatile unsigned long mem_error_addr;
145#define CRIME_MEM_ERROR_ADDR_MASK 0x3fffffff
146
147 volatile unsigned long mem_ecc_syn;
148#define CRIME_MEM_ERROR_ECC_SYN_MASK 0xffffffff
149
150 volatile unsigned long mem_ecc_chk;
151#define CRIME_MEM_ERROR_ECC_CHK_MASK 0xffffffff
152
153 volatile unsigned long mem_ecc_repl;
154#define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff
155};
156
157extern struct sgi_crime *crime;
158
159#define CRIME_HI_MEM_BASE 0x40000000 /* this is where whole 1G of RAM is mapped */
160
161#endif /* __ASM_CRIME_H__ */
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
new file mode 100644
index 000000000000..c3c280e3d591
--- /dev/null
+++ b/include/asm-mips/ip32/ip32_ints.h
@@ -0,0 +1,94 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000 Harald Koerfgen
7 */
8
9#ifndef __ASM_IP32_INTS_H
10#define __ASM_IP32_INTS_H
11
12/*
13 * This list reflects the assignment of interrupt numbers to
14 * interrupting events. Order is fairly irrelevant to handling
15 * priority. This differs from irix.
16 */
17
18/* CPU */
19#define IP32_R4K_TIMER_IRQ 0
20
21/* MACE */
22#define MACE_VID_IN1_IRQ 1
23#define MACE_VID_IN2_IRQ 2
24#define MACE_VID_OUT_IRQ 3
25#define MACE_ETHERNET_IRQ 4
26/* SUPERIO, MISC, and AUDIO are MACEISA */
27#define MACE_PCI_BRIDGE_IRQ 8
28
29/* MACEPCI */
30#define MACEPCI_SCSI0_IRQ 9
31#define MACEPCI_SCSI1_IRQ 10
32#define MACEPCI_SLOT0_IRQ 11
33#define MACEPCI_SLOT1_IRQ 12
34#define MACEPCI_SLOT2_IRQ 13
35#define MACEPCI_SHARED0_IRQ 14
36#define MACEPCI_SHARED1_IRQ 15
37#define MACEPCI_SHARED2_IRQ 16
38
39/* CRIME */
40#define CRIME_GBE0_IRQ 17
41#define CRIME_GBE1_IRQ 18
42#define CRIME_GBE2_IRQ 19
43#define CRIME_GBE3_IRQ 20
44#define CRIME_CPUERR_IRQ 21
45#define CRIME_MEMERR_IRQ 22
46#define CRIME_RE_EMPTY_E_IRQ 23
47#define CRIME_RE_FULL_E_IRQ 24
48#define CRIME_RE_IDLE_E_IRQ 25
49#define CRIME_RE_EMPTY_L_IRQ 26
50#define CRIME_RE_FULL_L_IRQ 27
51#define CRIME_RE_IDLE_L_IRQ 28
52#define CRIME_SOFT0_IRQ 29
53#define CRIME_SOFT1_IRQ 30
54#define CRIME_SOFT2_IRQ 31
55#define CRIME_SYSCORERR_IRQ CRIME_SOFT2_IRQ
56#define CRIME_VICE_IRQ 32
57
58/* MACEISA */
59#define MACEISA_AUDIO_SW_IRQ 33
60#define MACEISA_AUDIO_SC_IRQ 34
61#define MACEISA_AUDIO1_DMAT_IRQ 35
62#define MACEISA_AUDIO1_OF_IRQ 36
63#define MACEISA_AUDIO2_DMAT_IRQ 37
64#define MACEISA_AUDIO2_MERR_IRQ 38
65#define MACEISA_AUDIO3_DMAT_IRQ 39
66#define MACEISA_AUDIO3_MERR_IRQ 40
67#define MACEISA_RTC_IRQ 41
68#define MACEISA_KEYB_IRQ 42
69/* MACEISA_KEYB_POLL is not an IRQ */
70#define MACEISA_MOUSE_IRQ 44
71/* MACEISA_MOUSE_POLL is not an IRQ */
72#define MACEISA_TIMER0_IRQ 46
73#define MACEISA_TIMER1_IRQ 47
74#define MACEISA_TIMER2_IRQ 48
75#define MACEISA_PARALLEL_IRQ 49
76#define MACEISA_PAR_CTXA_IRQ 50
77#define MACEISA_PAR_CTXB_IRQ 51
78#define MACEISA_PAR_MERR_IRQ 52
79#define MACEISA_SERIAL1_IRQ 53
80#define MACEISA_SERIAL1_TDMAT_IRQ 54
81#define MACEISA_SERIAL1_TDMAPR_IRQ 55
82#define MACEISA_SERIAL1_TDMAME_IRQ 56
83#define MACEISA_SERIAL1_RDMAT_IRQ 57
84#define MACEISA_SERIAL1_RDMAOR_IRQ 58
85#define MACEISA_SERIAL2_IRQ 59
86#define MACEISA_SERIAL2_TDMAT_IRQ 60
87#define MACEISA_SERIAL2_TDMAPR_IRQ 61
88#define MACEISA_SERIAL2_TDMAME_IRQ 62
89#define MACEISA_SERIAL2_RDMAT_IRQ 63
90#define MACEISA_SERIAL2_RDMAOR_IRQ 64
91
92#define IP32_IRQ_MAX MACEISA_SERIAL2_RDMAOR_IRQ
93
94#endif /* __ASM_IP32_INTS_H */
diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h
new file mode 100644
index 000000000000..2b7b0fdeac19
--- /dev/null
+++ b/include/asm-mips/ip32/mace.h
@@ -0,0 +1,334 @@
1/*
2 * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Harald Koerfgen
9 * Copyright (C) 2004 Ladislav Michl
10 */
11
12#ifndef __ASM_MACE_H__
13#define __ASM_MACE_H__
14
15/*
16 * Address map
17 */
18#define MACE_BASE 0x1f000000 /* physical */
19
20#undef BIT
21#define BIT(x) (1UL << (x))
22
23/*
24 * PCI interface
25 */
26struct mace_pci {
27 volatile unsigned int error_addr;
28 volatile unsigned int error;
29#define MACEPCI_ERROR_MASTER_ABORT BIT(31)
30#define MACEPCI_ERROR_TARGET_ABORT BIT(30)
31#define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29)
32#define MACEPCI_ERROR_RETRY_ERR BIT(28)
33#define MACEPCI_ERROR_ILLEGAL_CMD BIT(27)
34#define MACEPCI_ERROR_SYSTEM_ERR BIT(26)
35#define MACEPCI_ERROR_INTERRUPT_TEST BIT(25)
36#define MACEPCI_ERROR_PARITY_ERR BIT(24)
37#define MACEPCI_ERROR_OVERRUN BIT(23)
38#define MACEPCI_ERROR_RSVD BIT(22)
39#define MACEPCI_ERROR_MEMORY_ADDR BIT(21)
40#define MACEPCI_ERROR_CONFIG_ADDR BIT(20)
41#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID BIT(19)
42#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID BIT(18)
43#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID BIT(17)
44#define MACEPCI_ERROR_RETRY_ADDR_VALID BIT(16)
45#define MACEPCI_ERROR_SIG_TABORT BIT(4)
46#define MACEPCI_ERROR_DEVSEL_MASK 0xc0
47#define MACEPCI_ERROR_DEVSEL_FAST 0
48#define MACEPCI_ERROR_DEVSEL_MED 0x40
49#define MACEPCI_ERROR_DEVSEL_SLOW 0x80
50#define MACEPCI_ERROR_FBB BIT(1)
51#define MACEPCI_ERROR_66MHZ BIT(0)
52 volatile unsigned int control;
53#define MACEPCI_CONTROL_INT(x) BIT(x)
54#define MACEPCI_CONTROL_INT_MASK 0xff
55#define MACEPCI_CONTROL_SERR_ENA BIT(8)
56#define MACEPCI_CONTROL_ARB_N6 BIT(9)
57#define MACEPCI_CONTROL_PARITY_ERR BIT(10)
58#define MACEPCI_CONTROL_MRMRA_ENA BIT(11)
59#define MACEPCI_CONTROL_ARB_N3 BIT(12)
60#define MACEPCI_CONTROL_ARB_N4 BIT(13)
61#define MACEPCI_CONTROL_ARB_N5 BIT(14)
62#define MACEPCI_CONTROL_PARK_LIU BIT(15)
63#define MACEPCI_CONTROL_INV_INT(x) BIT(16+x)
64#define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000
65#define MACEPCI_CONTROL_OVERRUN_INT BIT(24)
66#define MACEPCI_CONTROL_PARITY_INT BIT(25)
67#define MACEPCI_CONTROL_SERR_INT BIT(26)
68#define MACEPCI_CONTROL_IT_INT BIT(27)
69#define MACEPCI_CONTROL_RE_INT BIT(28)
70#define MACEPCI_CONTROL_DPED_INT BIT(29)
71#define MACEPCI_CONTROL_TAR_INT BIT(30)
72#define MACEPCI_CONTROL_MAR_INT BIT(31)
73 volatile unsigned int rev;
74 unsigned int _pad[0xcf8/4 - 4];
75 volatile unsigned int config_addr;
76 union {
77 volatile unsigned char b[4];
78 volatile unsigned short w[2];
79 volatile unsigned int l;
80 } config_data;
81};
82#define MACEPCI_LOW_MEMORY 0x1a000000
83#define MACEPCI_LOW_IO 0x18000000
84#define MACEPCI_SWAPPED_VIEW 0
85#define MACEPCI_NATIVE_VIEW 0x40000000
86#define MACEPCI_IO 0x80000000
87#define MACEPCI_HI_MEMORY 0x280000000
88#define MACEPCI_HI_IO 0x100000000
89
90/*
91 * Video interface
92 */
93struct mace_video {
94 unsigned long xxx; /* later... */
95};
96
97/*
98 * Ethernet interface
99 */
100struct mace_ethernet {
101 volatile unsigned long mac_ctrl;
102 volatile unsigned long int_stat;
103 volatile unsigned long dma_ctrl;
104 volatile unsigned long timer;
105 volatile unsigned long tx_int_al;
106 volatile unsigned long rx_int_al;
107 volatile unsigned long tx_info;
108 volatile unsigned long tx_info_al;
109 volatile unsigned long rx_buff;
110 volatile unsigned long rx_buff_al1;
111 volatile unsigned long rx_buff_al2;
112 volatile unsigned long diag;
113 volatile unsigned long phy_data;
114 volatile unsigned long phy_regs;
115 volatile unsigned long phy_trans_go;
116 volatile unsigned long backoff_seed;
117 /*===================================*/
118 volatile unsigned long imq_reserved[4];
119 volatile unsigned long mac_addr;
120 volatile unsigned long mac_addr2;
121 volatile unsigned long mcast_filter;
122 volatile unsigned long tx_ring_base;
123 /* Following are read-only registers for debugging */
124 volatile unsigned long tx_pkt1_hdr;
125 volatile unsigned long tx_pkt1_ptr[3];
126 volatile unsigned long tx_pkt2_hdr;
127 volatile unsigned long tx_pkt2_ptr[3];
128 /*===================================*/
129 volatile unsigned long rx_fifo;
130};
131
132/*
133 * Peripherals
134 */
135
136/* Audio registers */
137struct mace_audio {
138 volatile unsigned long control;
139 volatile unsigned long codec_control; /* codec status control */
140 volatile unsigned long codec_mask; /* codec status input mask */
141 volatile unsigned long codec_read; /* codec status read data */
142 struct {
143 volatile unsigned long control; /* channel control */
144 volatile unsigned long read_ptr; /* channel read pointer */
145 volatile unsigned long write_ptr; /* channel write pointer */
146 volatile unsigned long depth; /* channel depth */
147 } chan[3];
148};
149
150/* ISA Control and DMA registers */
151struct mace_isactrl {
152 volatile unsigned long ringbase;
153#define MACEISA_RINGBUFFERS_SIZE (8 * 4096)
154
155 volatile unsigned long misc;
156#define MACEISA_FLASH_WE BIT(0) /* 1=> Enable FLASH writes */
157#define MACEISA_PWD_CLEAR BIT(1) /* 1=> PWD CLEAR jumper detected */
158#define MACEISA_NIC_DEASSERT BIT(2)
159#define MACEISA_NIC_DATA BIT(3)
160#define MACEISA_LED_RED BIT(4) /* 0=> Illuminate red LED */
161#define MACEISA_LED_GREEN BIT(5) /* 0=> Illuminate green LED */
162#define MACEISA_DP_RAM_ENABLE BIT(6)
163
164 volatile unsigned long istat;
165 volatile unsigned long imask;
166#define MACEISA_AUDIO_SW_INT BIT(0)
167#define MACEISA_AUDIO_SC_INT BIT(1)
168#define MACEISA_AUDIO1_DMAT_INT BIT(2)
169#define MACEISA_AUDIO1_OF_INT BIT(3)
170#define MACEISA_AUDIO2_DMAT_INT BIT(4)
171#define MACEISA_AUDIO2_MERR_INT BIT(5)
172#define MACEISA_AUDIO3_DMAT_INT BIT(6)
173#define MACEISA_AUDIO3_MERR_INT BIT(7)
174#define MACEISA_RTC_INT BIT(8)
175#define MACEISA_KEYB_INT BIT(9)
176#define MACEISA_KEYB_POLL_INT BIT(10)
177#define MACEISA_MOUSE_INT BIT(11)
178#define MACEISA_MOUSE_POLL_INT BIT(12)
179#define MACEISA_TIMER0_INT BIT(13)
180#define MACEISA_TIMER1_INT BIT(14)
181#define MACEISA_TIMER2_INT BIT(15)
182#define MACEISA_PARALLEL_INT BIT(16)
183#define MACEISA_PAR_CTXA_INT BIT(17)
184#define MACEISA_PAR_CTXB_INT BIT(18)
185#define MACEISA_PAR_MERR_INT BIT(19)
186#define MACEISA_SERIAL1_INT BIT(20)
187#define MACEISA_SERIAL1_TDMAT_INT BIT(21)
188#define MACEISA_SERIAL1_TDMAPR_INT BIT(22)
189#define MACEISA_SERIAL1_TDMAME_INT BIT(23)
190#define MACEISA_SERIAL1_RDMAT_INT BIT(24)
191#define MACEISA_SERIAL1_RDMAOR_INT BIT(25)
192#define MACEISA_SERIAL2_INT BIT(26)
193#define MACEISA_SERIAL2_TDMAT_INT BIT(27)
194#define MACEISA_SERIAL2_TDMAPR_INT BIT(28)
195#define MACEISA_SERIAL2_TDMAME_INT BIT(29)
196#define MACEISA_SERIAL2_RDMAT_INT BIT(30)
197#define MACEISA_SERIAL2_RDMAOR_INT BIT(31)
198
199 volatile unsigned long _pad[0x2000/8 - 4];
200
201 volatile unsigned long dp_ram[0x400];
202};
203
204/* Keyboard & Mouse registers
205 * -> drivers/input/serio/maceps2.c */
206struct mace_ps2port {
207 volatile unsigned long tx;
208 volatile unsigned long rx;
209 volatile unsigned long control;
210 volatile unsigned long status;
211};
212
213struct mace_ps2 {
214 struct mace_ps2port keyb;
215 struct mace_ps2port mouse;
216};
217
218/* I2C registers
219 * -> drivers/i2c/algos/i2c-algo-sgi.c */
220struct mace_i2c {
221 volatile unsigned long config;
222#define MACEI2C_RESET BIT(0)
223#define MACEI2C_FAST BIT(1)
224#define MACEI2C_DATA_OVERRIDE BIT(2)
225#define MACEI2C_CLOCK_OVERRIDE BIT(3)
226#define MACEI2C_DATA_STATUS BIT(4)
227#define MACEI2C_CLOCK_STATUS BIT(5)
228 volatile unsigned long control;
229 volatile unsigned long data;
230};
231
232/* Timer registers */
233typedef union {
234 volatile unsigned long ust_msc;
235 struct reg {
236 volatile unsigned int ust;
237 volatile unsigned int msc;
238 } reg;
239} timer_reg;
240
241struct mace_timers {
242 volatile unsigned long ust;
243#define MACE_UST_PERIOD_NS 960
244
245 volatile unsigned long compare1;
246 volatile unsigned long compare2;
247 volatile unsigned long compare3;
248
249 timer_reg audio_in;
250 timer_reg audio_out1;
251 timer_reg audio_out2;
252 timer_reg video_in1;
253 timer_reg video_in2;
254 timer_reg video_out;
255};
256
257struct mace_perif {
258 struct mace_audio audio;
259 char _pad0[0x10000 - sizeof(struct mace_audio)];
260
261 struct mace_isactrl ctrl;
262 char _pad1[0x10000 - sizeof(struct mace_isactrl)];
263
264 struct mace_ps2 ps2;
265 char _pad2[0x10000 - sizeof(struct mace_ps2)];
266
267 struct mace_i2c i2c;
268 char _pad3[0x10000 - sizeof(struct mace_i2c)];
269
270 struct mace_timers timers;
271 char _pad4[0x10000 - sizeof(struct mace_timers)];
272};
273
274
275/*
276 * ISA peripherals
277 */
278
279/* Parallel port */
280struct mace_parallel { /* later... */
281};
282
283struct mace_ecp1284 { /* later... */
284};
285
286/* Serial port */
287struct mace_serial {
288 volatile unsigned long xxx; /* later... */
289};
290
291struct mace_isa {
292 struct mace_parallel parallel;
293 char _pad1[0x8000 - sizeof(struct mace_parallel)];
294
295 struct mace_ecp1284 ecp1284;
296 char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
297
298 struct mace_serial serial1;
299 char _pad3[0x8000 - sizeof(struct mace_serial)];
300
301 struct mace_serial serial2;
302 char _pad4[0x8000 - sizeof(struct mace_serial)];
303
304 volatile unsigned char rtc[0x10000];
305};
306
307struct sgi_mace {
308 char _reserved[0x80000];
309
310 struct mace_pci pci;
311 char _pad0[0x80000 - sizeof(struct mace_pci)];
312
313 struct mace_video video_in1;
314 char _pad1[0x80000 - sizeof(struct mace_video)];
315
316 struct mace_video video_in2;
317 char _pad2[0x80000 - sizeof(struct mace_video)];
318
319 struct mace_video video_out;
320 char _pad3[0x80000 - sizeof(struct mace_video)];
321
322 struct mace_ethernet eth;
323 char _pad4[0x80000 - sizeof(struct mace_ethernet)];
324
325 struct mace_perif perif;
326 char _pad5[0x80000 - sizeof(struct mace_perif)];
327
328 struct mace_isa isa;
329 char _pad6[0x80000 - sizeof(struct mace_isa)];
330};
331
332extern struct sgi_mace *mace;
333
334#endif /* __ASM_MACE_H__ */
diff --git a/include/asm-mips/ip32/machine.h b/include/asm-mips/ip32/machine.h
new file mode 100644
index 000000000000..e440fdf4b232
--- /dev/null
+++ b/include/asm-mips/ip32/machine.h
@@ -0,0 +1,21 @@
1/*
2 * machine.h -- Machine/group probing for ip32
3 *
4 * Copyright (C) 2001 Keith M Wesolowski
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10#ifndef _ASM_IP32_MACHINE_H
11#define _ASM_IP32_MACHINE_H
12
13#include <linux/config.h>
14
15#ifdef CONFIG_SGI_IP32
16
17#define SGI_MACH_O2 0x3201
18
19#endif /* CONFIG_SGI_IP32 */
20
21#endif /* _ASM_SGI_MACHINE_H */