1 files changed, 26 insertions, 16 deletions
diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h
index 5bdc51d85b6c..e514efe44c06 100644
--- a/include/asm-mips/ip32/mace.h
+++ b/include/asm-mips/ip32/mace.h
@@ -150,24 +150,34 @@ struct mace_audio {
 /* register definitions for parallel port DMA */
 struct mace_parport {
-/* 0 - do nothing, 1 - pulse terminal count to the device after buffer is drained */ 
+        /* 0 - do nothing,
-#define MACEPAR_CONTEXT_LASTFLAG BIT(63)
+         * 1 - pulse terminal count to the device after buffer is drained */
-/* Should not cross 4K page boundary */
+#define MACEPAR_CONTEXT_LASTFLAG        BIT(63)
-#define MACEPAR_CONTEXT_DATALEN_MASK 0xfff00000000
+        /* Should not cross 4K page boundary */
-/* Can be arbitrarily aligned on any byte boundary on output, 64 byte aligned on input */
+#define MACEPAR_CONTEXT_DATA_BOUND      0x0000000000001000UL
-#define MACEPAR_CONTEXT_BASEADDR_MASK 0xffffffff
+#define MACEPAR_CONTEXT_DATALEN_MASK    0x00000fff00000000UL
+#define MACEPAR_CONTEXT_DATALEN_SHIFT   32
+        /* Can be arbitrarily aligned on any byte boundary on output,
+         * 64 byte aligned on input */
+#define MACEPAR_CONTEXT_BASEADDR_MASK   0x00000000ffffffffUL
        volatile u64 context_a;
        volatile u64 context_b;
-#define MACEPAR_CTLSTAT_DIRECTION BIT(0) /* 0 - mem->device, 1 - device->mem */
+        /* 0 - mem->device, 1 - device->mem */
-#define MACEPAR_CTLSTAT_ENABLE BIT(1) /* 0 - channel frozen, 1 - channel enabled */
+#define MACEPAR_CTLSTAT_DIRECTION       BIT(0)
-#define MACEPAR_CTLSTAT_RESET BIT(2) /* 0 - channel active, 1 - complete channel reset */
+        /* 0 - channel frozen, 1 - channel enabled */
-#define MACEPAR_CTLSTAT_CTXB_VALID BIT(3)
+#define MACEPAR_CTLSTAT_ENABLE          BIT(1)
-#define MACEPAR_CTLSTAT_CTXA_VALID BIT(4)
+        /* 0 - channel active, 1 - complete channel reset */
-        volatile u64 cntlstat; /* Control/Status register */
+#define MACEPAR_CTLSTAT_RESET           BIT(2)
-#define MACEPAR_DIAG_CTXINUSE BIT(1)
+#define MACEPAR_CTLSTAT_CTXB_VALID      BIT(3)
-#define MACEPAR_DIAG_DMACTIVE BIT(2) /* 1 - Dma engine is enabled and processing something */
+#define MACEPAR_CTLSTAT_CTXA_VALID      BIT(4)
-#define MACEPAR_DIAG_CTRMASK 0x3ffc /* Counter of bytes left */
+        volatile u64 cntlstat;          /* Control/Status register */
-        volatile u64 diagnostic; /* RO: diagnostic register */
+#define MACEPAR_DIAG_CTXINUSE           BIT(0)
+        /* 1 - Dma engine is enabled and processing something */
+#define MACEPAR_DIAG_DMACTIVE           BIT(1)
+        /* Counter of bytes left */
+#define MACEPAR_DIAG_CTRMASK            0x0000000000003ffcUL
+#define MACEPAR_DIAG_CTRSHIFT           2
+        volatile u64 diagnostic;        /* RO: diagnostic register */
 };
 /* ISA Control and DMA registers */

diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h index 5bdc51d85b6c..e514efe44c06 100644 --- a/include/asm-mips/ip32/mace.h +++ b/include/asm-mips/ip32/mace.h
@@ -150,24 +150,34 @@ struct mace_audio {
150		150
151	/* register definitions for parallel port DMA */	151	/* register definitions for parallel port DMA */
152	struct mace_parport {	152	struct mace_parport {
153	/* 0 - do nothing, 1 - pulse terminal count to the device after buffer is drained */	153	/* 0 - do nothing,
154	#define MACEPAR_CONTEXT_LASTFLAG BIT(63)	154	* 1 - pulse terminal count to the device after buffer is drained */
155	/* Should not cross 4K page boundary */	155	#define MACEPAR_CONTEXT_LASTFLAG BIT(63)
156	#define MACEPAR_CONTEXT_DATALEN_MASK 0xfff00000000	156	/* Should not cross 4K page boundary */
157	/* Can be arbitrarily aligned on any byte boundary on output, 64 byte aligned on input */	157	#define MACEPAR_CONTEXT_DATA_BOUND 0x0000000000001000UL
158	#define MACEPAR_CONTEXT_BASEADDR_MASK 0xffffffff	158	#define MACEPAR_CONTEXT_DATALEN_MASK 0x00000fff00000000UL
		159	#define MACEPAR_CONTEXT_DATALEN_SHIFT 32
		160	/* Can be arbitrarily aligned on any byte boundary on output,
		161	* 64 byte aligned on input */
		162	#define MACEPAR_CONTEXT_BASEADDR_MASK 0x00000000ffffffffUL
159	volatile u64 context_a;	163	volatile u64 context_a;
160	volatile u64 context_b;	164	volatile u64 context_b;
161	#define MACEPAR_CTLSTAT_DIRECTION BIT(0) /* 0 - mem->device, 1 - device->mem */	165	/* 0 - mem->device, 1 - device->mem */
162	#define MACEPAR_CTLSTAT_ENABLE BIT(1) /* 0 - channel frozen, 1 - channel enabled */	166	#define MACEPAR_CTLSTAT_DIRECTION BIT(0)
163	#define MACEPAR_CTLSTAT_RESET BIT(2) /* 0 - channel active, 1 - complete channel reset */	167	/* 0 - channel frozen, 1 - channel enabled */
164	#define MACEPAR_CTLSTAT_CTXB_VALID BIT(3)	168	#define MACEPAR_CTLSTAT_ENABLE BIT(1)
165	#define MACEPAR_CTLSTAT_CTXA_VALID BIT(4)	169	/* 0 - channel active, 1 - complete channel reset */
166	volatile u64 cntlstat; /* Control/Status register */	170	#define MACEPAR_CTLSTAT_RESET BIT(2)
167	#define MACEPAR_DIAG_CTXINUSE BIT(1)	171	#define MACEPAR_CTLSTAT_CTXB_VALID BIT(3)
168	#define MACEPAR_DIAG_DMACTIVE BIT(2) /* 1 - Dma engine is enabled and processing something */	172	#define MACEPAR_CTLSTAT_CTXA_VALID BIT(4)
169	#define MACEPAR_DIAG_CTRMASK 0x3ffc /* Counter of bytes left */	173	volatile u64 cntlstat; /* Control/Status register */
170	volatile u64 diagnostic; /* RO: diagnostic register */	174	#define MACEPAR_DIAG_CTXINUSE BIT(0)
		175	/* 1 - Dma engine is enabled and processing something */
		176	#define MACEPAR_DIAG_DMACTIVE BIT(1)
		177	/* Counter of bytes left */
		178	#define MACEPAR_DIAG_CTRMASK 0x0000000000003ffcUL
		179	#define MACEPAR_DIAG_CTRSHIFT 2
		180	volatile u64 diagnostic; /* RO: diagnostic register */
171	};	181	};
172		182
173	/* ISA Control and DMA registers */	183	/* ISA Control and DMA registers */