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-rw-r--r--include/asm-mips/interrupt.h27
1 files changed, 19 insertions, 8 deletions
diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h
index abdf54ee64cf..774348734fa0 100644
--- a/include/asm-mips/interrupt.h
+++ b/include/asm-mips/interrupt.h
@@ -47,6 +47,17 @@ static inline void local_irq_enable(void)
47 * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs 47 * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
48 * no nops at all. 48 * no nops at all.
49 */ 49 */
50/*
51 * For TX49, operating only IE bit is not enough.
52 *
53 * If mfc0 $12 follows store and the mfc0 is last instruction of a
54 * page and fetching the next instruction causes TLB miss, the result
55 * of the mfc0 might wrongly contain EXL bit.
56 *
57 * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
58 *
59 * Workaround: mask EXL bit of the result or place a nop before mfc0.
60 */
50__asm__ ( 61__asm__ (
51 " .macro local_irq_disable\n" 62 " .macro local_irq_disable\n"
52 " .set push \n" 63 " .set push \n"
@@ -55,8 +66,8 @@ __asm__ (
55 " di \n" 66 " di \n"
56#else 67#else
57 " mfc0 $1,$12 \n" 68 " mfc0 $1,$12 \n"
58 " ori $1,1 \n" 69 " ori $1,0x1f \n"
59 " xori $1,1 \n" 70 " xori $1,0x1f \n"
60 " .set noreorder \n" 71 " .set noreorder \n"
61 " mtc0 $1,$12 \n" 72 " mtc0 $1,$12 \n"
62#endif 73#endif
@@ -96,8 +107,8 @@ __asm__ (
96 " andi \\result, 1 \n" 107 " andi \\result, 1 \n"
97#else 108#else
98 " mfc0 \\result, $12 \n" 109 " mfc0 \\result, $12 \n"
99 " ori $1, \\result, 1 \n" 110 " ori $1, \\result, 0x1f \n"
100 " xori $1, 1 \n" 111 " xori $1, 0x1f \n"
101 " .set noreorder \n" 112 " .set noreorder \n"
102 " mtc0 $1, $12 \n" 113 " mtc0 $1, $12 \n"
103#endif 114#endif
@@ -114,6 +125,7 @@ __asm__ __volatile__( \
114 125
115__asm__ ( 126__asm__ (
116 " .macro local_irq_restore flags \n" 127 " .macro local_irq_restore flags \n"
128 " .set push \n"
117 " .set noreorder \n" 129 " .set noreorder \n"
118 " .set noat \n" 130 " .set noat \n"
119#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) 131#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
@@ -135,14 +147,13 @@ __asm__ (
135#else 147#else
136 " mfc0 $1, $12 \n" 148 " mfc0 $1, $12 \n"
137 " andi \\flags, 1 \n" 149 " andi \\flags, 1 \n"
138 " ori $1, 1 \n" 150 " ori $1, 0x1f \n"
139 " xori $1, 1 \n" 151 " xori $1, 0x1f \n"
140 " or \\flags, $1 \n" 152 " or \\flags, $1 \n"
141 " mtc0 \\flags, $12 \n" 153 " mtc0 \\flags, $12 \n"
142#endif 154#endif
143 " irq_disable_hazard \n" 155 " irq_disable_hazard \n"
144 " .set at \n" 156 " .set pop \n"
145 " .set reorder \n"
146 " .endm \n"); 157 " .endm \n");
147 158
148#define local_irq_restore(flags) \ 159#define local_irq_restore(flags) \