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Diffstat (limited to 'include/asm-mips/i8259.h')
-rw-r--r--include/asm-mips/i8259.h37
1 files changed, 29 insertions, 8 deletions
diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h
index 0214abe3f0af..4df8d8b118c0 100644
--- a/include/asm-mips/i8259.h
+++ b/include/asm-mips/i8259.h
@@ -19,10 +19,31 @@
19 19
20#include <asm/io.h> 20#include <asm/io.h>
21 21
22/* i8259A PIC registers */
23#define PIC_MASTER_CMD 0x20
24#define PIC_MASTER_IMR 0x21
25#define PIC_MASTER_ISR PIC_MASTER_CMD
26#define PIC_MASTER_POLL PIC_MASTER_ISR
27#define PIC_MASTER_OCW3 PIC_MASTER_ISR
28#define PIC_SLAVE_CMD 0xa0
29#define PIC_SLAVE_IMR 0xa1
30
31/* i8259A PIC related value */
32#define PIC_CASCADE_IR 2
33#define MASTER_ICW4_DEFAULT 0x01
34#define SLAVE_ICW4_DEFAULT 0x01
35#define PIC_ICW4_AEOI 2
36
22extern spinlock_t i8259A_lock; 37extern spinlock_t i8259A_lock;
23 38
39extern void init_8259A(int auto_eoi);
40extern void enable_8259A_irq(unsigned int irq);
41extern void disable_8259A_irq(unsigned int irq);
42
24extern void init_i8259_irqs(void); 43extern void init_i8259_irqs(void);
25 44
45#define I8259A_IRQ_BASE 0
46
26/* 47/*
27 * Do the traditional i8259 interrupt polling thing. This is for the few 48 * Do the traditional i8259 interrupt polling thing. This is for the few
28 * cases where no better interrupt acknowledge method is available and we 49 * cases where no better interrupt acknowledge method is available and we
@@ -35,15 +56,15 @@ static inline int i8259_irq(void)
35 spin_lock(&i8259A_lock); 56 spin_lock(&i8259A_lock);
36 57
37 /* Perform an interrupt acknowledge cycle on controller 1. */ 58 /* Perform an interrupt acknowledge cycle on controller 1. */
38 outb(0x0C, 0x20); /* prepare for poll */ 59 outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */
39 irq = inb(0x20) & 7; 60 irq = inb(PIC_MASTER_CMD) & 7;
40 if (irq == 2) { 61 if (irq == PIC_CASCADE_IR) {
41 /* 62 /*
42 * Interrupt is cascaded so perform interrupt 63 * Interrupt is cascaded so perform interrupt
43 * acknowledge on controller 2. 64 * acknowledge on controller 2.
44 */ 65 */
45 outb(0x0C, 0xA0); /* prepare for poll */ 66 outb(0x0C, PIC_SLAVE_CMD); /* prepare for poll */
46 irq = (inb(0xA0) & 7) + 8; 67 irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
47 } 68 }
48 69
49 if (unlikely(irq == 7)) { 70 if (unlikely(irq == 7)) {
@@ -54,14 +75,14 @@ static inline int i8259_irq(void)
54 * significant bit is not set then there is no valid 75 * significant bit is not set then there is no valid
55 * interrupt. 76 * interrupt.
56 */ 77 */
57 outb(0x0B, 0x20); /* ISR register */ 78 outb(0x0B, PIC_MASTER_ISR); /* ISR register */
58 if(~inb(0x20) & 0x80) 79 if(~inb(PIC_MASTER_ISR) & 0x80)
59 irq = -1; 80 irq = -1;
60 } 81 }
61 82
62 spin_unlock(&i8259A_lock); 83 spin_unlock(&i8259A_lock);
63 84
64 return irq; 85 return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
65} 86}
66 87
67#endif /* _ASM_I8259_H */ 88#endif /* _ASM_I8259_H */