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Diffstat (limited to 'include/asm-mips/gcmpregs.h')
| -rw-r--r-- | include/asm-mips/gcmpregs.h | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/include/asm-mips/gcmpregs.h b/include/asm-mips/gcmpregs.h new file mode 100644 index 000000000000..d74a8a4ca861 --- /dev/null +++ b/include/asm-mips/gcmpregs.h | |||
| @@ -0,0 +1,117 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2000, 07 MIPS Technologies, Inc. | ||
| 7 | * | ||
| 8 | * Multiprocessor Subsystem Register Definitions | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_GCMPREGS_H | ||
| 12 | #define _ASM_GCMPREGS_H | ||
| 13 | |||
| 14 | |||
| 15 | /* Offsets to major blocks within GCMP from GCMP base */ | ||
| 16 | #define GCMP_GCB_OFS 0x0000 /* Global Control Block */ | ||
| 17 | #define GCMP_CLCB_OFS 0x2000 /* Core Local Control Block */ | ||
| 18 | #define GCMP_COCB_OFS 0x4000 /* Core Other Control Block */ | ||
| 19 | #define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ | ||
| 20 | |||
| 21 | /* Offsets to individual GCMP registers from GCMP base */ | ||
| 22 | #define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) | ||
| 23 | |||
| 24 | #define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) | ||
| 25 | #define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) | ||
| 26 | #define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) | ||
| 27 | #define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) | ||
| 28 | |||
| 29 | /* GCMP register access */ | ||
| 30 | #define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) | ||
| 31 | #define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) | ||
| 32 | #define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) | ||
| 33 | #define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) | ||
| 34 | |||
| 35 | /* Mask generation */ | ||
| 36 | #define GCMPMSK(block, reg, bits) (MSK(bits)<<GCMP_##block##_##reg##_SHF) | ||
| 37 | #define GCMPGCBMSK(reg, bits) GCMPMSK(GCB, reg, bits) | ||
| 38 | #define GCMPCCBMSK(reg, bits) GCMPMSK(CCB, reg, bits) | ||
| 39 | #define GCMPGDBMSK(reg, bits) GCMPMSK(GDB, reg, bits) | ||
| 40 | |||
| 41 | /* GCB registers */ | ||
| 42 | #define GCMP_GCB_GC_OFS 0x0000 /* Global Config Register */ | ||
| 43 | #define GCMP_GCB_GC_NUMIOCU_SHF 8 | ||
| 44 | #define GCMP_GCB_GC_NUMIOCU_MSK GCMPGCBMSK(GC_NUMIOCU, 4) | ||
| 45 | #define GCMP_GCB_GC_NUMCORES_SHF 0 | ||
| 46 | #define GCMP_GCB_GC_NUMCORES_MSK GCMPGCBMSK(GC_NUMCORES, 8) | ||
| 47 | #define GCMP_GCB_GCMPB_OFS 0x0008 /* Global GCMP Base */ | ||
| 48 | #define GCMP_GCB_GCMPB_GCMPBASE_SHF 15 | ||
| 49 | #define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) | ||
| 50 | #define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 | ||
| 51 | #define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) | ||
| 52 | #define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0 | ||
| 53 | #define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1 | ||
| 54 | #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 | ||
| 55 | #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 | ||
| 56 | #define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ | ||
| 57 | #define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ | ||
| 58 | #define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 | ||
| 59 | #define GCMP_GCB_GCSRAP_CMACCESS_MSK GCMPGCBMSK(GCSRAP_CMACCESS, 8) | ||
| 60 | #define GCMP_GCB_GCMPREV_OFS 0x0030 /* GCMP Revision Register */ | ||
| 61 | #define GCMP_GCB_GCMEM_OFS 0x0040 /* Global CM Error Mask */ | ||
| 62 | #define GCMP_GCB_GCMEC_OFS 0x0048 /* Global CM Error Cause */ | ||
| 63 | #define GCMP_GCB_GMEC_ERROR_TYPE_SHF 27 | ||
| 64 | #define GCMP_GCB_GMEC_ERROR_TYPE_MSK GCMPGCBMSK(GMEC_ERROR_TYPE, 5) | ||
| 65 | #define GCMP_GCB_GMEC_ERROR_INFO_SHF 0 | ||
| 66 | #define GCMP_GCB_GMEC_ERROR_INFO_MSK GCMPGCBMSK(GMEC_ERROR_INFO, 27) | ||
| 67 | #define GCMP_GCB_GCMEA_OFS 0x0050 /* Global CM Error Address */ | ||
| 68 | #define GCMP_GCB_GCMEO_OFS 0x0058 /* Global CM Error Multiple */ | ||
| 69 | #define GCMP_GCB_GMEO_ERROR_2ND_SHF 0 | ||
| 70 | #define GCMP_GCB_GMEO_ERROR_2ND_MSK GCMPGCBMSK(GMEO_ERROR_2ND, 5) | ||
| 71 | #define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */ | ||
| 72 | #define GCMP_GCB_GICBA_BASE_SHF 17 | ||
| 73 | #define GCMP_GCB_GICBA_BASE_MSK GCMPGCBMSK(GICBA_BASE, 15) | ||
| 74 | #define GCMP_GCB_GICBA_EN_SHF 0 | ||
| 75 | #define GCMP_GCB_GICBA_EN_MSK GCMPGCBMSK(GICBA_EN, 1) | ||
| 76 | |||
| 77 | /* GCB Regions */ | ||
| 78 | #define GCMP_GCB_CMxBASE_OFS(n) (0x0090+16*(n)) /* Global Region[0-3] Base Address */ | ||
| 79 | #define GCMP_GCB_CMxBASE_BASE_SHF 16 | ||
| 80 | #define GCMP_GCB_CMxBASE_BASE_MSK GCMPGCBMSK(CMxBASE_BASE, 16) | ||
| 81 | #define GCMP_GCB_CMxMASK_OFS(n) (0x0098+16*(n)) /* Global Region[0-3] Address Mask */ | ||
| 82 | #define GCMP_GCB_CMxMASK_MASK_SHF 16 | ||
| 83 | #define GCMP_GCB_CMxMASK_MASK_MSK GCMPGCBMSK(CMxMASK_MASK, 16) | ||
| 84 | #define GCMP_GCB_CMxMASK_CMREGTGT_SHF 0 | ||
| 85 | #define GCMP_GCB_CMxMASK_CMREGTGT_MSK GCMPGCBMSK(CMxMASK_CMREGTGT, 2) | ||
| 86 | #define GCMP_GCB_CMxMASK_CMREGTGT_MEM 0 | ||
| 87 | #define GCMP_GCB_CMxMASK_CMREGTGT_MEM1 1 | ||
| 88 | #define GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2 | ||
| 89 | #define GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3 | ||
| 90 | |||
| 91 | |||
| 92 | /* Core local/Core other control block registers */ | ||
| 93 | #define GCMP_CCB_RESETR_OFS 0x0000 /* Reset Release */ | ||
| 94 | #define GCMP_CCB_RESETR_INRESET_SHF 0 | ||
| 95 | #define GCMP_CCB_RESETR_INRESET_MSK GCMPCCBMSK(RESETR_INRESET, 16) | ||
| 96 | #define GCMP_CCB_COHCTL_OFS 0x0008 /* Coherence Control */ | ||
| 97 | #define GCMP_CCB_COHCTL_DOMAIN_SHF 0 | ||
| 98 | #define GCMP_CCB_COHCTL_DOMAIN_MSK GCMPCCBMSK(COHCTL_DOMAIN, 8) | ||
| 99 | #define GCMP_CCB_CFG_OFS 0x0010 /* Config */ | ||
| 100 | #define GCMP_CCB_CFG_IOCUTYPE_SHF 10 | ||
| 101 | #define GCMP_CCB_CFG_IOCUTYPE_MSK GCMPCCBMSK(CFG_IOCUTYPE, 2) | ||
| 102 | #define GCMP_CCB_CFG_IOCUTYPE_CPU 0 | ||
| 103 | #define GCMP_CCB_CFG_IOCUTYPE_NCIOCU 1 | ||
| 104 | #define GCMP_CCB_CFG_IOCUTYPE_CIOCU 2 | ||
| 105 | #define GCMP_CCB_CFG_NUMVPE_SHF 0 | ||
| 106 | #define GCMP_CCB_CFG_NUMVPE_MSK GCMPCCBMSK(CFG_NUMVPE, 10) | ||
| 107 | #define GCMP_CCB_OTHER_OFS 0x0018 /* Other Address */ | ||
| 108 | #define GCMP_CCB_OTHER_CORENUM_SHF 16 | ||
| 109 | #define GCMP_CCB_OTHER_CORENUM_MSK GCMPCCBMSK(OTHER_CORENUM, 16) | ||
| 110 | #define GCMP_CCB_RESETBASE_OFS 0x0020 /* Reset Exception Base */ | ||
| 111 | #define GCMP_CCB_RESETBASE_BEV_SHF 12 | ||
| 112 | #define GCMP_CCB_RESETBASE_BEV_MSK GCMPCCBMSK(RESETBASE_BEV, 20) | ||
| 113 | #define GCMP_CCB_ID_OFS 0x0028 /* Identification */ | ||
| 114 | #define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */ | ||
| 115 | #define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ | ||
| 116 | |||
| 117 | #endif /* _ASM_GCMPREGS_H */ | ||