diff options
Diffstat (limited to 'include/asm-mips/emma2rh')
-rw-r--r-- | include/asm-mips/emma2rh/emma2rh.h | 5 | ||||
-rw-r--r-- | include/asm-mips/emma2rh/markeins.h | 1 |
2 files changed, 4 insertions, 2 deletions
diff --git a/include/asm-mips/emma2rh/emma2rh.h b/include/asm-mips/emma2rh/emma2rh.h index 4fb8df71caa9..6a1af0af51e3 100644 --- a/include/asm-mips/emma2rh/emma2rh.h +++ b/include/asm-mips/emma2rh/emma2rh.h | |||
@@ -24,6 +24,8 @@ | |||
24 | #ifndef __ASM_EMMA2RH_EMMA2RH_H | 24 | #ifndef __ASM_EMMA2RH_EMMA2RH_H |
25 | #define __ASM_EMMA2RH_EMMA2RH_H | 25 | #define __ASM_EMMA2RH_EMMA2RH_H |
26 | 26 | ||
27 | #include <irq.h> | ||
28 | |||
27 | /* | 29 | /* |
28 | * EMMA2RH registers | 30 | * EMMA2RH registers |
29 | */ | 31 | */ |
@@ -104,7 +106,8 @@ | |||
104 | #define NUM_EMMA2RH_IRQ 96 | 106 | #define NUM_EMMA2RH_IRQ 96 |
105 | 107 | ||
106 | #define CPU_EMMA2RH_CASCADE 2 | 108 | #define CPU_EMMA2RH_CASCADE 2 |
107 | #define EMMA2RH_IRQ_BASE 0 | 109 | #define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE |
110 | #define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) | ||
108 | 111 | ||
109 | /* | 112 | /* |
110 | * emma2rh irq defs | 113 | * emma2rh irq defs |
diff --git a/include/asm-mips/emma2rh/markeins.h b/include/asm-mips/emma2rh/markeins.h index 8fa766795078..973b0628490d 100644 --- a/include/asm-mips/emma2rh/markeins.h +++ b/include/asm-mips/emma2rh/markeins.h | |||
@@ -33,7 +33,6 @@ | |||
33 | 33 | ||
34 | #define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ) | 34 | #define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ) |
35 | #define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW) | 35 | #define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW) |
36 | #define CPU_IRQ_BASE (EMMA2RH_GPIO_IRQ_BASE + NUM_EMMA2RH_IRQ_GPIO) | ||
37 | 36 | ||
38 | #define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE) | 37 | #define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE) |
39 | #define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE) | 38 | #define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE) |