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-rw-r--r--include/asm-mips/dec/kn02xa.h46
1 files changed, 28 insertions, 18 deletions
diff --git a/include/asm-mips/dec/kn02xa.h b/include/asm-mips/dec/kn02xa.h
index 648c4dcbba1d..a25f3d7da7f7 100644
--- a/include/asm-mips/dec/kn02xa.h
+++ b/include/asm-mips/dec/kn02xa.h
@@ -9,7 +9,7 @@
9 * 9 *
10 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions 10 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
11 * are by courtesy of Chris Fraser. 11 * are by courtesy of Chris Fraser.
12 * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki 12 * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
13 * 13 *
14 * These are addresses which have to be known early in the boot process. 14 * These are addresses which have to be known early in the boot process.
15 * For other addresses refer to tc.h, ioasic_addrs.h and friends. 15 * For other addresses refer to tc.h, ioasic_addrs.h and friends.
@@ -17,31 +17,23 @@
17#ifndef __ASM_MIPS_DEC_KN02XA_H 17#ifndef __ASM_MIPS_DEC_KN02XA_H
18#define __ASM_MIPS_DEC_KN02XA_H 18#define __ASM_MIPS_DEC_KN02XA_H
19 19
20#include <asm/addrspace.h>
21#include <asm/dec/ioasic_addrs.h> 20#include <asm/dec/ioasic_addrs.h>
22 21
23#define KN02XA_SLOT_BASE KSEG1ADDR(0x1c000000) 22#define KN02XA_SLOT_BASE 0x1c000000
24
25/*
26 * Some port addresses...
27 */
28#define KN02XA_IOASIC_BASE (KN02XA_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
29#define KN02XA_RTC_BASE (KN02XA_SLOT_BASE + IOASIC_TOY) /* RTC */
30
31 23
32/* 24/*
33 * Memory control ASIC registers. 25 * Memory control ASIC registers.
34 */ 26 */
35#define KN02XA_MER KSEG1ADDR(0x0c400000) /* memory error register */ 27#define KN02XA_MER 0x0c400000 /* memory error register */
36#define KN02XA_MSR KSEG1ADDR(0x0c800000) /* memory size register */ 28#define KN02XA_MSR 0x0c800000 /* memory size register */
37 29
38/* 30/*
39 * CPU control ASIC registers. 31 * CPU control ASIC registers.
40 */ 32 */
41#define KN02XA_MEM_CONF KSEG1ADDR(0x0e000000) /* write timeout config */ 33#define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */
42#define KN02XA_EAR KSEG1ADDR(0x0e000004) /* error address register */ 34#define KN02XA_EAR 0x0e000004 /* error address register */
43#define KN02XA_BOOT0 KSEG1ADDR(0x0e000008) /* boot 0 register */ 35#define KN02XA_BOOT0 0x0e000008 /* boot 0 register */
44#define KN02XA_MEM_INTR KSEG1ADDR(0x0e00000c) /* write err IRQ stat & ack */ 36#define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */
45 37
46/* 38/*
47 * Memory Error Register bits, common definitions. 39 * Memory Error Register bits, common definitions.
@@ -52,8 +44,13 @@
52#define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */ 44#define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */
53#define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */ 45#define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */
54#define KN02XA_MER_PARDIS (1<<14) /* parity error disable */ 46#define KN02XA_MER_PARDIS (1<<14) /* parity error disable */
55#define KN02XA_MER_RES_12 (0x3<<12) /* unused */ 47#define KN02XA_MER_SIZE (1<<13) /* r/o mirror of MSR_SIZE */
56#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask */ 48#define KN02XA_MER_RES_12 (1<<12) /* unused */
49#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */
50#define KN02XA_MER_BYTERR_3 (0x8<<8) /* byte lane #3 */
51#define KN02XA_MER_BYTERR_2 (0x4<<8) /* byte lane #2 */
52#define KN02XA_MER_BYTERR_1 (0x2<<8) /* byte lane #1 */
53#define KN02XA_MER_BYTERR_0 (0x1<<8) /* byte lane #0 */
57#define KN02XA_MER_RES_0 (0xff<<0) /* unused */ 54#define KN02XA_MER_RES_0 (0xff<<0) /* unused */
58 55
59/* 56/*
@@ -72,4 +69,17 @@
72#define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */ 69#define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */
73#define KN02XA_EAR_RES_0 (0x3<<0) /* unused */ 70#define KN02XA_EAR_RES_0 (0x3<<0) /* unused */
74 71
72
73#ifndef __ASSEMBLY__
74
75#include <linux/interrupt.h>
76
77struct pt_regs;
78
79extern void dec_kn02xa_be_init(void);
80extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup);
81extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
82 struct pt_regs *regs);
83#endif
84
75#endif /* __ASM_MIPS_DEC_KN02XA_H */ 85#endif /* __ASM_MIPS_DEC_KN02XA_H */