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-rw-r--r--include/asm-mips/cpu-info.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 94f1c8172360..0c5a358863f3 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -54,6 +54,8 @@ struct cpuinfo_mips {
54 struct cache_desc dcache; /* Primary D or combined I/D cache */ 54 struct cache_desc dcache; /* Primary D or combined I/D cache */
55 struct cache_desc scache; /* Secondary cache */ 55 struct cache_desc scache; /* Secondary cache */
56 struct cache_desc tcache; /* Tertiary/split secondary cache */ 56 struct cache_desc tcache; /* Tertiary/split secondary cache */
57 int srsets; /* Shadow register sets */
58 int core; /* physical core number */
57#if defined(CONFIG_MIPS_MT_SMTC) 59#if defined(CONFIG_MIPS_MT_SMTC)
58 /* 60 /*
59 * In the MIPS MT "SMTC" model, each TC is considered 61 * In the MIPS MT "SMTC" model, each TC is considered
@@ -62,8 +64,10 @@ struct cpuinfo_mips {
62 * to all TCs within the same VPE. 64 * to all TCs within the same VPE.
63 */ 65 */
64 int vpe_id; /* Virtual Processor number */ 66 int vpe_id; /* Virtual Processor number */
65 int tc_id; /* Thread Context number */
66#endif /* CONFIG_MIPS_MT */ 67#endif /* CONFIG_MIPS_MT */
68#ifdef CONFIG_MIPS_MT_SMTC
69 int tc_id; /* Thread Context number */
70#endif
67 void *data; /* Additional data */ 71 void *data; /* Additional data */
68} __attribute__((aligned(SMP_CACHE_BYTES))); 72} __attribute__((aligned(SMP_CACHE_BYTES)));
69 73