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-rw-r--r--include/asm-mips/cpu-info.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 140be1c67da7..6572ac703662 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -73,6 +73,16 @@ struct cpuinfo_mips {
73 struct cache_desc dcache; /* Primary D or combined I/D cache */ 73 struct cache_desc dcache; /* Primary D or combined I/D cache */
74 struct cache_desc scache; /* Secondary cache */ 74 struct cache_desc scache; /* Secondary cache */
75 struct cache_desc tcache; /* Tertiary/split secondary cache */ 75 struct cache_desc tcache; /* Tertiary/split secondary cache */
76#if defined(CONFIG_MIPS_MT_SMTC)
77 /*
78 * In the MIPS MT "SMTC" model, each TC is considered
79 * to be a "CPU" for the purposes of scheduling, but
80 * exception resources, ASID spaces, etc, are common
81 * to all TCs within the same VPE.
82 */
83 int vpe_id; /* Virtual Processor number */
84 int tc_id; /* Thread Context number */
85#endif /* CONFIG_MIPS_MT */
76 void *data; /* Additional data */ 86 void *data; /* Additional data */
77} __attribute__((aligned(SMP_CACHE_BYTES))); 87} __attribute__((aligned(SMP_CACHE_BYTES)));
78 88