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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 */
11#ifndef __ASM_CPU_INFO_H
12#define __ASM_CPU_INFO_H
13
14#include <linux/config.h>
15#include <asm/cache.h>
16
17#ifdef CONFIG_SGI_IP27
18#include <asm/sn/types.h>
19#endif
20
21/*
22 * Descriptor for a cache
23 */
24struct cache_desc {
25 unsigned short linesz; /* Size of line in bytes */
26 unsigned short ways; /* Number of ways */
27 unsigned short sets; /* Number of lines per set */
28 unsigned int waysize; /* Bytes per way */
29 unsigned int waybit; /* Bits to select in a cache set */
30 unsigned int flags; /* Flags describing cache properties */
31};
32
33/*
34 * Flag definitions
35 */
36#define MIPS_CACHE_NOT_PRESENT 0x00000001
37#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
38#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
39#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
40#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
41
42struct cpuinfo_mips {
43 unsigned long udelay_val;
44 unsigned long asid_cache;
45#if defined(CONFIG_SGI_IP27)
46// cpuid_t p_cpuid; /* PROM assigned cpuid */
47 cnodeid_t p_nodeid; /* my node ID in compact-id-space */
48 nasid_t p_nasid; /* my node ID in numa-as-id-space */
49 unsigned char p_slice; /* Physical position on node board */
50#endif
51#if 0
52 unsigned long loops_per_sec;
53 unsigned long ipi_count;
54 unsigned long irq_attempt[NR_IRQS];
55 unsigned long smp_local_irq_count;
56 unsigned long prof_multiplier;
57 unsigned long prof_counter;
58#endif
59
60 /*
61 * Capability and feature descriptor structure for MIPS CPU
62 */
63 unsigned long options;
64 unsigned int processor_id;
65 unsigned int fpu_id;
66 unsigned int cputype;
67 int isa_level;
68 int tlbsize;
69 struct cache_desc icache; /* Primary I-cache */
70 struct cache_desc dcache; /* Primary D or combined I/D cache */
71 struct cache_desc scache; /* Secondary cache */
72 struct cache_desc tcache; /* Tertiary/split secondary cache */
73 void *data; /* Additional data */
74} __attribute__((aligned(SMP_CACHE_BYTES)));
75
76extern struct cpuinfo_mips cpu_data[];
77#define current_cpu_data cpu_data[smp_processor_id()]
78
79extern void cpu_probe(void);
80extern void cpu_report(void);
81
82#endif /* __ASM_CPU_INFO_H */