diff options
Diffstat (limited to 'include/asm-mips/cpu-features.h')
-rw-r--r-- | include/asm-mips/cpu-features.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 4930824a43aa..bb2212cf460a 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h | |||
@@ -109,17 +109,6 @@ | |||
109 | #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) | 109 | #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) |
110 | #endif | 110 | #endif |
111 | 111 | ||
112 | /* | ||
113 | * Certain CPUs may throw bizarre exceptions if not the whole cacheline | ||
114 | * contains valid instructions. For these we ensure proper alignment of | ||
115 | * signal trampolines and pad them to the size of a full cache lines with | ||
116 | * nops. This is also used in structure definitions so can't be a test macro | ||
117 | * like the others. | ||
118 | */ | ||
119 | #ifndef PLAT_TRAMPOLINE_STUFF_LINE | ||
120 | #define PLAT_TRAMPOLINE_STUFF_LINE 0UL | ||
121 | #endif | ||
122 | |||
123 | #ifdef CONFIG_32BIT | 112 | #ifdef CONFIG_32BIT |
124 | # ifndef cpu_has_nofpuex | 113 | # ifndef cpu_has_nofpuex |
125 | # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) | 114 | # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) |