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-rw-r--r--include/asm-mips/bcache.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/include/asm-mips/bcache.h b/include/asm-mips/bcache.h
index 446102b34f4e..3646a3f2ed38 100644
--- a/include/asm-mips/bcache.h
+++ b/include/asm-mips/bcache.h
@@ -9,7 +9,6 @@
9#ifndef _ASM_BCACHE_H 9#ifndef _ASM_BCACHE_H
10#define _ASM_BCACHE_H 10#define _ASM_BCACHE_H
11 11
12#include <linux/config.h>
13 12
14/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent, 13/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
15 chipset implemented caches. On machines with other CPUs the CPU does the 14 chipset implemented caches. On machines with other CPUs the CPU does the