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Diffstat (limited to 'include/asm-mips/addrspace.h')
-rw-r--r-- | include/asm-mips/addrspace.h | 187 |
1 files changed, 187 insertions, 0 deletions
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h new file mode 100644 index 000000000000..2caa8c427204 --- /dev/null +++ b/include/asm-mips/addrspace.h | |||
@@ -0,0 +1,187 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 1996, 99 Ralf Baechle | ||
7 | * Copyright (C) 2000, 2002 Maciej W. Rozycki | ||
8 | * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. | ||
9 | */ | ||
10 | #ifndef _ASM_ADDRSPACE_H | ||
11 | #define _ASM_ADDRSPACE_H | ||
12 | |||
13 | #include <linux/config.h> | ||
14 | #include <spaces.h> | ||
15 | |||
16 | /* | ||
17 | * Configure language | ||
18 | */ | ||
19 | #ifdef __ASSEMBLY__ | ||
20 | #define _ATYPE_ | ||
21 | #define _ATYPE32_ | ||
22 | #define _ATYPE64_ | ||
23 | #else | ||
24 | #define _ATYPE_ __PTRDIFF_TYPE__ | ||
25 | #define _ATYPE32_ int | ||
26 | #define _ATYPE64_ long long | ||
27 | #endif | ||
28 | |||
29 | /* | ||
30 | * 32-bit MIPS address spaces | ||
31 | */ | ||
32 | #ifdef __ASSEMBLY__ | ||
33 | #define _ACAST32_ | ||
34 | #define _ACAST64_ | ||
35 | #else | ||
36 | #define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ | ||
37 | #define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ | ||
38 | #endif | ||
39 | |||
40 | /* | ||
41 | * Returns the kernel segment base of a given address | ||
42 | */ | ||
43 | #define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) | ||
44 | |||
45 | /* | ||
46 | * Returns the physical address of a CKSEGx / XKPHYS address | ||
47 | */ | ||
48 | #define CPHYSADDR(a) ((_ACAST32_ (a)) & 0x1fffffff) | ||
49 | #define XPHYSADDR(a) ((_ACAST64_ (a)) & 0x000000ffffffffff) | ||
50 | |||
51 | #ifdef CONFIG_MIPS64 | ||
52 | |||
53 | /* | ||
54 | * Memory segments (64bit kernel mode addresses) | ||
55 | * The compatibility segments use the full 64-bit sign extended value. Note | ||
56 | * the R8000 doesn't have them so don't reference these in generic MIPS code. | ||
57 | */ | ||
58 | #define XKUSEG 0x0000000000000000 | ||
59 | #define XKSSEG 0x4000000000000000 | ||
60 | #define XKPHYS 0x8000000000000000 | ||
61 | #define XKSEG 0xc000000000000000 | ||
62 | #define CKSEG0 0xffffffff80000000 | ||
63 | #define CKSEG1 0xffffffffa0000000 | ||
64 | #define CKSSEG 0xffffffffc0000000 | ||
65 | #define CKSEG3 0xffffffffe0000000 | ||
66 | |||
67 | #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) | ||
68 | #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) | ||
69 | #define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) | ||
70 | #define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) | ||
71 | |||
72 | #else | ||
73 | |||
74 | #define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) | ||
75 | #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) | ||
76 | #define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) | ||
77 | #define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) | ||
78 | |||
79 | /* | ||
80 | * Map an address to a certain kernel segment | ||
81 | */ | ||
82 | #define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) | ||
83 | #define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) | ||
84 | #define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) | ||
85 | #define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) | ||
86 | |||
87 | /* | ||
88 | * Memory segments (32bit kernel mode addresses) | ||
89 | * These are the traditional names used in the 32-bit universe. | ||
90 | */ | ||
91 | #define KUSEG 0x00000000 | ||
92 | #define KSEG0 0x80000000 | ||
93 | #define KSEG1 0xa0000000 | ||
94 | #define KSEG2 0xc0000000 | ||
95 | #define KSEG3 0xe0000000 | ||
96 | |||
97 | #define CKUSEG 0x00000000 | ||
98 | #define CKSEG0 0x80000000 | ||
99 | #define CKSEG1 0xa0000000 | ||
100 | #define CKSEG2 0xc0000000 | ||
101 | #define CKSEG3 0xe0000000 | ||
102 | |||
103 | #endif | ||
104 | |||
105 | /* | ||
106 | * Cache modes for XKPHYS address conversion macros | ||
107 | */ | ||
108 | #define K_CALG_COH_EXCL1_NOL2 0 | ||
109 | #define K_CALG_COH_SHRL1_NOL2 1 | ||
110 | #define K_CALG_UNCACHED 2 | ||
111 | #define K_CALG_NONCOHERENT 3 | ||
112 | #define K_CALG_COH_EXCL 4 | ||
113 | #define K_CALG_COH_SHAREABLE 5 | ||
114 | #define K_CALG_NOTUSED 6 | ||
115 | #define K_CALG_UNCACHED_ACCEL 7 | ||
116 | |||
117 | /* | ||
118 | * 64-bit address conversions | ||
119 | */ | ||
120 | #define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) | ||
121 | #define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) | ||
122 | #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) | ||
123 | #define PHYS_TO_XKPHYS(cm,a) (0x8000000000000000 | ((cm)<<59) | (a)) | ||
124 | |||
125 | #if defined (CONFIG_CPU_R4300) \ | ||
126 | || defined (CONFIG_CPU_R4X00) \ | ||
127 | || defined (CONFIG_CPU_R5000) \ | ||
128 | || defined (CONFIG_CPU_NEVADA) \ | ||
129 | || defined (CONFIG_CPU_TX49XX) \ | ||
130 | || defined (CONFIG_CPU_MIPS64) | ||
131 | #define KUSIZE 0x0000010000000000 /* 2^^40 */ | ||
132 | #define KUSIZE_64 0x0000010000000000 /* 2^^40 */ | ||
133 | #define K0SIZE 0x0000001000000000 /* 2^^36 */ | ||
134 | #define K1SIZE 0x0000001000000000 /* 2^^36 */ | ||
135 | #define K2SIZE 0x000000ff80000000 | ||
136 | #define KSEGSIZE 0x000000ff80000000 /* max syssegsz */ | ||
137 | #define TO_PHYS_MASK 0x0000000fffffffff /* 2^^36 - 1 */ | ||
138 | #endif | ||
139 | |||
140 | #if defined (CONFIG_CPU_R8000) | ||
141 | /* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */ | ||
142 | #define KUSIZE 0x0000010000000000 /* 2^^40 */ | ||
143 | #define KUSIZE_64 0x0000010000000000 /* 2^^40 */ | ||
144 | #define K0SIZE 0x0000010000000000 /* 2^^40 */ | ||
145 | #define K1SIZE 0x0000010000000000 /* 2^^40 */ | ||
146 | #define K2SIZE 0x0001000000000000 | ||
147 | #define KSEGSIZE 0x0000010000000000 /* max syssegsz */ | ||
148 | #define TO_PHYS_MASK 0x000000ffffffffff /* 2^^40 - 1 */ | ||
149 | #endif | ||
150 | |||
151 | #if defined (CONFIG_CPU_R10000) | ||
152 | #define KUSIZE 0x0000010000000000 /* 2^^40 */ | ||
153 | #define KUSIZE_64 0x0000010000000000 /* 2^^40 */ | ||
154 | #define K0SIZE 0x0000010000000000 /* 2^^40 */ | ||
155 | #define K1SIZE 0x0000010000000000 /* 2^^40 */ | ||
156 | #define K2SIZE 0x00000fff80000000 | ||
157 | #define KSEGSIZE 0x00000fff80000000 /* max syssegsz */ | ||
158 | #define TO_PHYS_MASK 0x000000ffffffffff /* 2^^40 - 1 */ | ||
159 | #endif | ||
160 | |||
161 | /* | ||
162 | * Further names for SGI source compatibility. These are stolen from | ||
163 | * IRIX's <sys/mips_addrspace.h>. | ||
164 | */ | ||
165 | #define KUBASE 0 | ||
166 | #define KUSIZE_32 0x0000000080000000 /* KUSIZE | ||
167 | for a 32 bit proc */ | ||
168 | #define K0BASE_EXL_WR 0xa800000000000000 /* exclusive on write */ | ||
169 | #define K0BASE_NONCOH 0x9800000000000000 /* noncoherent */ | ||
170 | #define K0BASE_EXL 0xa000000000000000 /* exclusive */ | ||
171 | |||
172 | #ifndef CONFIG_CPU_R8000 | ||
173 | |||
174 | /* | ||
175 | * The R8000 doesn't have the 32-bit compat spaces so we don't define them | ||
176 | * in order to catch bugs in the source code. | ||
177 | */ | ||
178 | |||
179 | #define COMPAT_K1BASE32 0xffffffffa0000000 | ||
180 | #define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ | ||
181 | |||
182 | #endif | ||
183 | |||
184 | #define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) | ||
185 | #define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) | ||
186 | |||
187 | #endif /* _ASM_ADDRSPACE_H */ | ||