diff options
Diffstat (limited to 'include/asm-m68knommu/mcfcache.h')
| -rw-r--r-- | include/asm-m68knommu/mcfcache.h | 125 |
1 files changed, 125 insertions, 0 deletions
diff --git a/include/asm-m68knommu/mcfcache.h b/include/asm-m68knommu/mcfcache.h new file mode 100644 index 000000000000..bdd8c53ef34c --- /dev/null +++ b/include/asm-m68knommu/mcfcache.h | |||
| @@ -0,0 +1,125 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * mcfcache.h -- ColdFire CPU cache support code | ||
| 5 | * | ||
| 6 | * (C) Copyright 2004, Greg Ungerer <gerg@snapgear.com> | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | #ifndef __M68KNOMMU_MCFCACHE_H | ||
| 11 | #define __M68KNOMMU_MCFCACHE_H | ||
| 12 | /****************************************************************************/ | ||
| 13 | |||
| 14 | #include <linux/config.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * The different ColdFire families have different cache arrangments. | ||
| 18 | * Everything from a small instruction only cache, to configurable | ||
| 19 | * data and/or instruction cache, to unified instruction/data, to | ||
| 20 | * harvard style separate instruction and data caches. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) | ||
| 24 | /* | ||
| 25 | * Simple version 2 core cache. These have instruction cache only, | ||
| 26 | * we just need to invalidate it and enable it. | ||
| 27 | */ | ||
| 28 | .macro CACHE_ENABLE | ||
| 29 | movel #0x01000000,%d0 /* invalidate cache cmd */ | ||
| 30 | movec %d0,%CACR /* do invalidate cache */ | ||
| 31 | movel #0x80000100,%d0 /* setup cache mask */ | ||
| 32 | movec %d0,%CACR /* enable cache */ | ||
| 33 | .endm | ||
| 34 | #endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ | ||
| 35 | |||
| 36 | #if defined(CONFIG_M527x) | ||
| 37 | /* | ||
| 38 | * New version 2 cores have a configurable split cache arrangement. | ||
| 39 | * For now I am just enabling instruction cache - but ultimately I | ||
| 40 | * think a split instruction/data cache would be better. | ||
| 41 | */ | ||
| 42 | .macro CACHE_ENABLE | ||
| 43 | movel #0x01400000,%d0 | ||
| 44 | movec %d0,%CACR /* invalidate cache */ | ||
| 45 | nop | ||
| 46 | movel #0x0000c000,%d0 /* set SDRAM cached only */ | ||
| 47 | movec %d0,%ACR0 | ||
| 48 | movel #0x00000000,%d0 /* no other regions cached */ | ||
| 49 | movec %d0,%ACR1 | ||
| 50 | movel #0x80400100,%d0 /* configure cache */ | ||
| 51 | movec %d0,%CACR /* enable cache */ | ||
| 52 | nop | ||
| 53 | .endm | ||
| 54 | #endif /* CONFIG_M527x */ | ||
| 55 | |||
| 56 | #if defined(CONFIG_M528x) | ||
| 57 | /* | ||
| 58 | * Cache is totally broken on early 5282 silicon. So far now we | ||
| 59 | * disable its cache all together. | ||
| 60 | */ | ||
| 61 | .macro CACHE_ENABLE | ||
| 62 | movel #0x01000000,%d0 | ||
| 63 | movec %d0,%CACR /* invalidate cache */ | ||
| 64 | nop | ||
| 65 | movel #0x0000c000,%d0 /* set SDRAM cached only */ | ||
| 66 | movec %d0,%ACR0 | ||
| 67 | movel #0x00000000,%d0 /* no other regions cached */ | ||
| 68 | movec %d0,%ACR1 | ||
| 69 | movel #0x00000000,%d0 /* configure cache */ | ||
| 70 | movec %d0,%CACR /* enable cache */ | ||
| 71 | nop | ||
| 72 | .endm | ||
| 73 | #endif /* CONFIG_M528x */ | ||
| 74 | |||
| 75 | #if defined(CONFIG_M5249) || defined(CONFIG_M5307) | ||
| 76 | /* | ||
| 77 | * The version 3 core cache. Oddly enough the version 2 core 5249 | ||
| 78 | * has the same SDRAM and cache setup as the version 3 cores. | ||
| 79 | * This is a single unified instruction/data cache. | ||
| 80 | */ | ||
| 81 | .macro CACHE_ENABLE | ||
| 82 | movel #0x01000000,%d0 /* invalidate whole cache */ | ||
| 83 | movec %d0,%CACR | ||
| 84 | nop | ||
| 85 | #if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3) | ||
| 86 | movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ | ||
| 87 | #else | ||
| 88 | movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */ | ||
| 89 | #endif | ||
| 90 | movec %d0,%ACR0 | ||
| 91 | movel #0x00000000,%d0 /* no other regions cached */ | ||
| 92 | movec %d0,%ACR1 | ||
| 93 | movel #0xa0000200,%d0 /* enable cache */ | ||
| 94 | movec %d0,%CACR | ||
| 95 | nop | ||
| 96 | .endm | ||
| 97 | #endif /* CONFIG_M5249 || CONFIG_M5307 */ | ||
| 98 | |||
| 99 | #if defined(CONFIG_M5407) | ||
| 100 | /* | ||
| 101 | * Version 4 cores have a true harvard style separate instruction | ||
| 102 | * and data cache. Invalidate and enable cache, also enable write | ||
| 103 | * buffers and branch accelerator. | ||
| 104 | */ | ||
| 105 | .macro CACHE_ENABLE | ||
| 106 | movel #0x01040100,%d0 /* invalidate whole cache */ | ||
| 107 | movec %d0,%CACR | ||
| 108 | nop | ||
| 109 | movel #0x000fc000,%d0 /* set SDRAM cached only */ | ||
| 110 | movec %d0, %ACR0 | ||
| 111 | movel #0x00000000,%d0 /* no other regions cached */ | ||
| 112 | movec %d0, %ACR1 | ||
| 113 | movel #0x000fc000,%d0 /* set SDRAM cached only */ | ||
| 114 | movec %d0, %ACR2 | ||
| 115 | movel #0x00000000,%d0 /* no other regions cached */ | ||
| 116 | movec %d0, %ACR3 | ||
| 117 | movel #0xb6088400,%d0 /* enable caches */ | ||
| 118 | movec %d0,%CACR | ||
| 119 | nop | ||
| 120 | .endm | ||
| 121 | #endif /* CONFIG_M5407 */ | ||
| 122 | |||
| 123 | |||
| 124 | /****************************************************************************/ | ||
| 125 | #endif /* __M68KNOMMU_MCFCACHE_H */ | ||