diff options
Diffstat (limited to 'include/asm-m68knommu/m5407sim.h')
| -rw-r--r-- | include/asm-m68knommu/m5407sim.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/asm-m68knommu/m5407sim.h b/include/asm-m68knommu/m5407sim.h index 75dcdacdb298..cc22c4a53005 100644 --- a/include/asm-m68knommu/m5407sim.h +++ b/include/asm-m68knommu/m5407sim.h | |||
| @@ -48,22 +48,22 @@ | |||
| 48 | #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ | 48 | #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ |
| 49 | #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ | 49 | #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ |
| 50 | 50 | ||
| 51 | #define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */ | 51 | #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ |
| 52 | #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ | 52 | #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ |
| 53 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ | 53 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ |
| 54 | #define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */ | 54 | #define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ |
| 55 | #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ | 55 | #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ |
| 56 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ | 56 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ |
| 57 | #define MCFSIM_CSAR4 0xb0 /* CS 4 Adress reg (r/w) */ | 57 | #define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ |
| 58 | #define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ | 58 | #define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ |
| 59 | #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ | 59 | #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ |
| 60 | #define MCFSIM_CSAR5 0xbc /* CS 5 Adress reg (r/w) */ | 60 | #define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ |
| 61 | #define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ | 61 | #define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ |
| 62 | #define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ | 62 | #define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ |
| 63 | #define MCFSIM_CSAR6 0xc8 /* CS 6 Adress reg (r/w) */ | 63 | #define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ |
| 64 | #define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ | 64 | #define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ |
| 65 | #define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ | 65 | #define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ |
| 66 | #define MCFSIM_CSAR7 0xd4 /* CS 7 Adress reg (r/w) */ | 66 | #define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ |
| 67 | #define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ | 67 | #define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ |
| 68 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ | 68 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ |
| 69 | 69 | ||