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diff --git a/include/asm-m68knommu/m5307sim.h b/include/asm-m68knommu/m5307sim.h
deleted file mode 100644
index 5886728409c0..000000000000
--- a/include/asm-m68knommu/m5307sim.h
+++ /dev/null
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1/****************************************************************************/
2
3/*
4 * m5307sim.h -- ColdFire 5307 System Integration Module support.
5 *
6 * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd.
7 * (C) Copyright 1999, Lineo (www.lineo.com)
8 *
9 * Modified by David W. Miller for the MCF5307 Eval Board.
10 */
11
12/****************************************************************************/
13#ifndef m5307sim_h
14#define m5307sim_h
15/****************************************************************************/
16
17/*
18 * Define the 5307 SIM register set addresses.
19 */
20#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
21#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
22#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
23#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
24#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
25#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
26#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/
27#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
28#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
29#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
30#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
31#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
32#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
33#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
34#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
35#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
36#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
37#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
38#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
39#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
40#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
41#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
42#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
43
44#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
45#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
46#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
47#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
48#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
49#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
50
51#ifdef CONFIG_OLDMASK
52#define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */
53#define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */
54#define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */
55#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
56#define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */
57#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
58#define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */
59#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
60#define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */
61#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
62#define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */
63#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
64#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */
65#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
66#else
67#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
68#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
69#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
70#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
71#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
72#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
73#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
74#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
75#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
76#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */
77#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
78#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
79#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */
80#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
81#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
82#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */
83#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
84#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
85#endif /* CONFIG_OLDMASK */
86
87#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
88#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
89#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
90#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
91#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
92
93#define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */
94#define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */
95
96
97/* Definition offset address for CS2-7 -- old mask 5307 */
98
99#define MCF5307_CS2 (0x400000)
100#define MCF5307_CS3 (0x600000)
101#define MCF5307_CS4 (0x800000)
102#define MCF5307_CS5 (0xA00000)
103#define MCF5307_CS6 (0xC00000)
104#define MCF5307_CS7 (0xE00000)
105
106
107/*
108 * Some symbol defines for the above...
109 */
110#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
111#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
112#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
113#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
114#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
115#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
116#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
117#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
118#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
119
120#if defined(CONFIG_M5307)
121#define MCFSIM_IMR_MASKALL 0x3fffe /* All SIM intr sources */
122#endif
123
124/*
125 * Macro to set IMR register. It is 32 bits on the 5307.
126 */
127#define mcf_getimr() \
128 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
129
130#define mcf_setimr(imr) \
131 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
132
133#define mcf_getipr() \
134 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
135
136
137/*
138 * Some symbol defines for the Parallel Port Pin Assignment Register
139 */
140#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
141 /* Clear to select par I/O */
142#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */
143 /* Clear to select par I/O */
144
145/*
146 * Defines for the IRQPAR Register
147 */
148#define IRQ5_LEVEL4 0x80
149#define IRQ3_LEVEL6 0x40
150#define IRQ1_LEVEL2 0x20
151
152
153/*
154 * Define the Cache register flags.
155 */
156#define CACR_EC (1<<31)
157#define CACR_ESB (1<<29)
158#define CACR_DPI (1<<28)
159#define CACR_HLCK (1<<27)
160#define CACR_CINVA (1<<24)
161#define CACR_DNFB (1<<10)
162#define CACR_DCM_WTHRU (0<<8)
163#define CACR_DCM_WBACK (1<<8)
164#define CACR_DCM_OFF_PRE (2<<8)
165#define CACR_DCM_OFF_IMP (3<<8)
166#define CACR_DW (1<<5)
167
168#define ACR_BASE_POS 24
169#define ACR_MASK_POS 16
170#define ACR_ENABLE (1<<15)
171#define ACR_USER (0<<13)
172#define ACR_SUPER (1<<13)
173#define ACR_ANY (2<<13)
174#define ACR_CM_WTHRU (0<<5)
175#define ACR_CM_WBACK (1<<5)
176#define ACR_CM_OFF_PRE (2<<5)
177#define ACR_CM_OFF_IMP (3<<5)
178#define ACR_WPROTECT (1<<2)
179
180/****************************************************************************/
181#endif /* m5307sim_h */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 00:55:31 -0500