diff options
Diffstat (limited to 'include/asm-m68knommu/m527xsim.h')
| -rw-r--r-- | include/asm-m68knommu/m527xsim.h | 74 |
1 files changed, 0 insertions, 74 deletions
diff --git a/include/asm-m68knommu/m527xsim.h b/include/asm-m68knommu/m527xsim.h deleted file mode 100644 index 1f63ab3fb3e6..000000000000 --- a/include/asm-m68knommu/m527xsim.h +++ /dev/null | |||
| @@ -1,74 +0,0 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | #ifndef m527xsim_h | ||
| 11 | #define m527xsim_h | ||
| 12 | /****************************************************************************/ | ||
| 13 | |||
| 14 | |||
| 15 | /* | ||
| 16 | * Define the 5270/5271 SIM register set addresses. | ||
| 17 | */ | ||
| 18 | #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ | ||
| 19 | #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */ | ||
| 20 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ | ||
| 21 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | ||
| 22 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | ||
| 23 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | ||
| 24 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | ||
| 25 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | ||
| 26 | #define MCFINTC_IRLR 0x18 /* */ | ||
| 27 | #define MCFINTC_IACKL 0x19 /* */ | ||
| 28 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | ||
| 29 | |||
| 30 | #define MCFINT_VECBASE 64 /* Vector base number */ | ||
| 31 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ | ||
| 32 | #define MCFINT_UART1 14 /* Interrupt number for UART1 */ | ||
| 33 | #define MCFINT_UART2 15 /* Interrupt number for UART2 */ | ||
| 34 | #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ | ||
| 35 | |||
| 36 | /* | ||
| 37 | * SDRAM configuration registers. | ||
| 38 | */ | ||
| 39 | #ifdef CONFIG_M5271 | ||
| 40 | #define MCFSIM_DCR 0x40 /* SDRAM control */ | ||
| 41 | #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ | ||
| 42 | #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ | ||
| 43 | #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ | ||
| 44 | #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ | ||
| 45 | #endif | ||
| 46 | #ifdef CONFIG_M5275 | ||
| 47 | #define MCFSIM_DMR 0x40 /* SDRAM mode */ | ||
| 48 | #define MCFSIM_DCR 0x44 /* SDRAM control */ | ||
| 49 | #define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ | ||
| 50 | #define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */ | ||
| 51 | #define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */ | ||
| 52 | #define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ | ||
| 53 | #define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */ | ||
| 54 | #define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ | ||
| 55 | #endif | ||
| 56 | |||
| 57 | /* | ||
| 58 | * GPIO pins setups to enable the UARTs. | ||
| 59 | */ | ||
| 60 | #ifdef CONFIG_M5271 | ||
| 61 | #define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ | ||
| 62 | #define UART0_ENABLE_MASK 0x000f | ||
| 63 | #define UART1_ENABLE_MASK 0x0ff0 | ||
| 64 | #define UART2_ENABLE_MASK 0x3000 | ||
| 65 | #endif | ||
| 66 | #ifdef CONFIG_M5275 | ||
| 67 | #define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ | ||
| 68 | #define UART0_ENABLE_MASK 0x000f | ||
| 69 | #define UART1_ENABLE_MASK 0x00f0 | ||
| 70 | #define UART2_ENABLE_MASK 0x3f00 | ||
| 71 | #endif | ||
| 72 | |||
| 73 | /****************************************************************************/ | ||
| 74 | #endif /* m527xsim_h */ | ||