diff options
Diffstat (limited to 'include/asm-m68knommu/m523xsim.h')
| -rw-r--r-- | include/asm-m68knommu/m523xsim.h | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/include/asm-m68knommu/m523xsim.h b/include/asm-m68knommu/m523xsim.h deleted file mode 100644 index bf397313e93f..000000000000 --- a/include/asm-m68knommu/m523xsim.h +++ /dev/null | |||
| @@ -1,45 +0,0 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * m523xsim.h -- ColdFire 523x System Integration Module support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com> | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | #ifndef m523xsim_h | ||
| 11 | #define m523xsim_h | ||
| 12 | /****************************************************************************/ | ||
| 13 | |||
| 14 | |||
| 15 | /* | ||
| 16 | * Define the 523x SIM register set addresses. | ||
| 17 | */ | ||
| 18 | #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ | ||
| 19 | #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ | ||
| 20 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ | ||
| 21 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | ||
| 22 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | ||
| 23 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | ||
| 24 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | ||
| 25 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | ||
| 26 | #define MCFINTC_IRLR 0x18 /* */ | ||
| 27 | #define MCFINTC_IACKL 0x19 /* */ | ||
| 28 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | ||
| 29 | |||
| 30 | #define MCFINT_VECBASE 64 /* Vector base number */ | ||
| 31 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ | ||
| 32 | #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ | ||
| 33 | #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ | ||
| 34 | |||
| 35 | /* | ||
| 36 | * SDRAM configuration registers. | ||
| 37 | */ | ||
| 38 | #define MCFSIM_DCR 0x44 /* SDRAM control */ | ||
| 39 | #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ | ||
| 40 | #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ | ||
| 41 | #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ | ||
| 42 | #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ | ||
| 43 | |||
| 44 | /****************************************************************************/ | ||
| 45 | #endif /* m523xsim_h */ | ||