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-rw-r--r--include/asm-m68knommu/m520xsim.h12
1 files changed, 11 insertions, 1 deletions
diff --git a/include/asm-m68knommu/m520xsim.h b/include/asm-m68knommu/m520xsim.h
index 1dac22ea95ba..49d016e6391a 100644
--- a/include/asm-m68knommu/m520xsim.h
+++ b/include/asm-m68knommu/m520xsim.h
@@ -31,6 +31,16 @@
31#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 31#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
32#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 32#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
33 33
34/*
35 * SDRAM configuration registers.
36 */
37#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */
38#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */
39#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */
40#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */
41#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
42#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
43
34 44
35#define MCF_GPIO_PAR_UART (0xA4036) 45#define MCF_GPIO_PAR_UART (0xA4036)
36#define MCF_GPIO_PAR_FECI2C (0xA4033) 46#define MCF_GPIO_PAR_FECI2C (0xA4033)
@@ -47,7 +57,7 @@
47 57
48#define ICR_INTRCONF 0x05 58#define ICR_INTRCONF 0x05
49#define MCFPIT_IMR MCFINTC_IMRL 59#define MCFPIT_IMR MCFINTC_IMRL
50#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1) 60#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1)
51 61
52/****************************************************************************/ 62/****************************************************************************/
53#endif /* m520xsim_h */ 63#endif /* m520xsim_h */