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-rw-r--r--include/asm-m68k/traps.h265
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diff --git a/include/asm-m68k/traps.h b/include/asm-m68k/traps.h
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1/*
2 * linux/include/asm/traps.h
3 *
4 * Copyright (C) 1993 Hamish Macdonald
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef _M68K_TRAPS_H
12#define _M68K_TRAPS_H
13
14#ifndef __ASSEMBLY__
15
16typedef void (*e_vector)(void);
17
18extern e_vector vectors[];
19
20#endif
21
22#define VEC_RESETSP (0)
23#define VEC_RESETPC (1)
24#define VEC_BUSERR (2)
25#define VEC_ADDRERR (3)
26#define VEC_ILLEGAL (4)
27#define VEC_ZERODIV (5)
28#define VEC_CHK (6)
29#define VEC_TRAP (7)
30#define VEC_PRIV (8)
31#define VEC_TRACE (9)
32#define VEC_LINE10 (10)
33#define VEC_LINE11 (11)
34#define VEC_RESV12 (12)
35#define VEC_COPROC (13)
36#define VEC_FORMAT (14)
37#define VEC_UNINT (15)
38#define VEC_RESV16 (16)
39#define VEC_RESV17 (17)
40#define VEC_RESV18 (18)
41#define VEC_RESV19 (19)
42#define VEC_RESV20 (20)
43#define VEC_RESV21 (21)
44#define VEC_RESV22 (22)
45#define VEC_RESV23 (23)
46#define VEC_SPUR (24)
47#define VEC_INT1 (25)
48#define VEC_INT2 (26)
49#define VEC_INT3 (27)
50#define VEC_INT4 (28)
51#define VEC_INT5 (29)
52#define VEC_INT6 (30)
53#define VEC_INT7 (31)
54#define VEC_SYS (32)
55#define VEC_TRAP1 (33)
56#define VEC_TRAP2 (34)
57#define VEC_TRAP3 (35)
58#define VEC_TRAP4 (36)
59#define VEC_TRAP5 (37)
60#define VEC_TRAP6 (38)
61#define VEC_TRAP7 (39)
62#define VEC_TRAP8 (40)
63#define VEC_TRAP9 (41)
64#define VEC_TRAP10 (42)
65#define VEC_TRAP11 (43)
66#define VEC_TRAP12 (44)
67#define VEC_TRAP13 (45)
68#define VEC_TRAP14 (46)
69#define VEC_TRAP15 (47)
70#define VEC_FPBRUC (48)
71#define VEC_FPIR (49)
72#define VEC_FPDIVZ (50)
73#define VEC_FPUNDER (51)
74#define VEC_FPOE (52)
75#define VEC_FPOVER (53)
76#define VEC_FPNAN (54)
77#define VEC_FPUNSUP (55)
78#define VEC_MMUCFG (56)
79#define VEC_MMUILL (57)
80#define VEC_MMUACC (58)
81#define VEC_RESV59 (59)
82#define VEC_UNIMPEA (60)
83#define VEC_UNIMPII (61)
84#define VEC_RESV62 (62)
85#define VEC_RESV63 (63)
86#define VEC_USER (64)
87
88#define VECOFF(vec) ((vec)<<2)
89
90#ifndef __ASSEMBLY__
91
92/* Status register bits */
93#define PS_T (0x8000)
94#define PS_S (0x2000)
95#define PS_M (0x1000)
96#define PS_C (0x0001)
97
98/* bits for 68020/68030 special status word */
99
100#define FC (0x8000)
101#define FB (0x4000)
102#define RC (0x2000)
103#define RB (0x1000)
104#define DF (0x0100)
105#define RM (0x0080)
106#define RW (0x0040)
107#define SZ (0x0030)
108#define DFC (0x0007)
109
110/* bits for 68030 MMU status register (mmusr,psr) */
111
112#define MMU_B (0x8000) /* bus error */
113#define MMU_L (0x4000) /* limit violation */
114#define MMU_S (0x2000) /* supervisor violation */
115#define MMU_WP (0x0800) /* write-protected */
116#define MMU_I (0x0400) /* invalid descriptor */
117#define MMU_M (0x0200) /* ATC entry modified */
118#define MMU_T (0x0040) /* transparent translation */
119#define MMU_NUM (0x0007) /* number of levels traversed */
120
121
122/* bits for 68040 special status word */
123#define CP_040 (0x8000)
124#define CU_040 (0x4000)
125#define CT_040 (0x2000)
126#define CM_040 (0x1000)
127#define MA_040 (0x0800)
128#define ATC_040 (0x0400)
129#define LK_040 (0x0200)
130#define RW_040 (0x0100)
131#define SIZ_040 (0x0060)
132#define TT_040 (0x0018)
133#define TM_040 (0x0007)
134
135/* bits for 68040 write back status word */
136#define WBV_040 (0x80)
137#define WBSIZ_040 (0x60)
138#define WBBYT_040 (0x20)
139#define WBWRD_040 (0x40)
140#define WBLNG_040 (0x00)
141#define WBTT_040 (0x18)
142#define WBTM_040 (0x07)
143
144/* bus access size codes */
145#define BA_SIZE_BYTE (0x20)
146#define BA_SIZE_WORD (0x40)
147#define BA_SIZE_LONG (0x00)
148#define BA_SIZE_LINE (0x60)
149
150/* bus access transfer type codes */
151#define BA_TT_MOVE16 (0x08)
152
153/* bits for 68040 MMU status register (mmusr) */
154#define MMU_B_040 (0x0800)
155#define MMU_G_040 (0x0400)
156#define MMU_S_040 (0x0080)
157#define MMU_CM_040 (0x0060)
158#define MMU_M_040 (0x0010)
159#define MMU_WP_040 (0x0004)
160#define MMU_T_040 (0x0002)
161#define MMU_R_040 (0x0001)
162
163/* bits in the 68060 fault status long word (FSLW) */
164#define MMU060_MA (0x08000000) /* misaligned */
165#define MMU060_LK (0x02000000) /* locked transfer */
166#define MMU060_RW (0x01800000) /* read/write */
167# define MMU060_RW_W (0x00800000) /* write */
168# define MMU060_RW_R (0x01000000) /* read */
169# define MMU060_RW_RMW (0x01800000) /* read/modify/write */
170# define MMU060_W (0x00800000) /* general write, includes rmw */
171#define MMU060_SIZ (0x00600000) /* transfer size */
172#define MMU060_TT (0x00180000) /* transfer type (TT) bits */
173#define MMU060_TM (0x00070000) /* transfer modifier (TM) bits */
174#define MMU060_IO (0x00008000) /* instruction or operand */
175#define MMU060_PBE (0x00004000) /* push buffer bus error */
176#define MMU060_SBE (0x00002000) /* store buffer bus error */
177#define MMU060_PTA (0x00001000) /* pointer A fault */
178#define MMU060_PTB (0x00000800) /* pointer B fault */
179#define MMU060_IL (0x00000400) /* double indirect descr fault */
180#define MMU060_PF (0x00000200) /* page fault (invalid descr) */
181#define MMU060_SP (0x00000100) /* supervisor protection */
182#define MMU060_WP (0x00000080) /* write protection */
183#define MMU060_TWE (0x00000040) /* bus error on table search */
184#define MMU060_RE (0x00000020) /* bus error on read */
185#define MMU060_WE (0x00000010) /* bus error on write */
186#define MMU060_TTR (0x00000008) /* error caused by TTR translation */
187#define MMU060_BPE (0x00000004) /* branch prediction error */
188#define MMU060_SEE (0x00000001) /* software emulated error */
189
190/* cases of missing or invalid descriptors */
191#define MMU060_DESC_ERR (MMU060_PTA | MMU060_PTB | \
192 MMU060_IL | MMU060_PF)
193/* bits that indicate real errors */
194#define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | MMU060_SP | \
195 MMU060_WP | MMU060_TWE | MMU060_RE | MMU060_WE)
196
197/* structure for stack frames */
198
199struct frame {
200 struct pt_regs ptregs;
201 union {
202 struct {
203 unsigned long iaddr; /* instruction address */
204 } fmt2;
205 struct {
206 unsigned long effaddr; /* effective address */
207 } fmt3;
208 struct {
209 unsigned long effaddr; /* effective address */
210 unsigned long pc; /* pc of faulted instr */
211 } fmt4;
212 struct {
213 unsigned long effaddr; /* effective address */
214 unsigned short ssw; /* special status word */
215 unsigned short wb3s; /* write back 3 status */
216 unsigned short wb2s; /* write back 2 status */
217 unsigned short wb1s; /* write back 1 status */
218 unsigned long faddr; /* fault address */
219 unsigned long wb3a; /* write back 3 address */
220 unsigned long wb3d; /* write back 3 data */
221 unsigned long wb2a; /* write back 2 address */
222 unsigned long wb2d; /* write back 2 data */
223 unsigned long wb1a; /* write back 1 address */
224 unsigned long wb1dpd0; /* write back 1 data/push data 0*/
225 unsigned long pd1; /* push data 1*/
226 unsigned long pd2; /* push data 2*/
227 unsigned long pd3; /* push data 3*/
228 } fmt7;
229 struct {
230 unsigned long iaddr; /* instruction address */
231 unsigned short int1[4]; /* internal registers */
232 } fmt9;
233 struct {
234 unsigned short int1;
235 unsigned short ssw; /* special status word */
236 unsigned short isc; /* instruction stage c */
237 unsigned short isb; /* instruction stage b */
238 unsigned long daddr; /* data cycle fault address */
239 unsigned short int2[2];
240 unsigned long dobuf; /* data cycle output buffer */
241 unsigned short int3[2];
242 } fmta;
243 struct {
244 unsigned short int1;
245 unsigned short ssw; /* special status word */
246 unsigned short isc; /* instruction stage c */
247 unsigned short isb; /* instruction stage b */
248 unsigned long daddr; /* data cycle fault address */
249 unsigned short int2[2];
250 unsigned long dobuf; /* data cycle output buffer */
251 unsigned short int3[4];
252 unsigned long baddr; /* stage B address */
253 unsigned short int4[2];
254 unsigned long dibuf; /* data cycle input buffer */
255 unsigned short int5[3];
256 unsigned ver : 4; /* stack frame version # */
257 unsigned int6:12;
258 unsigned short int7[18];
259 } fmtb;
260 } un;
261};
262
263#endif /* __ASSEMBLY__ */
264
265#endif /* _M68K_TRAPS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 08:43:36 -0500