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-rw-r--r--include/asm-m68k/pgtable.h166
1 files changed, 0 insertions, 166 deletions
diff --git a/include/asm-m68k/pgtable.h b/include/asm-m68k/pgtable.h
deleted file mode 100644
index 0b604f0f192d..000000000000
--- a/include/asm-m68k/pgtable.h
+++ /dev/null
@@ -1,166 +0,0 @@
1#ifndef _M68K_PGTABLE_H
2#define _M68K_PGTABLE_H
3
4#include <asm-generic/4level-fixup.h>
5
6#include <asm/setup.h>
7
8#ifndef __ASSEMBLY__
9#include <asm/processor.h>
10#include <linux/sched.h>
11#include <linux/threads.h>
12
13/*
14 * This file contains the functions and defines necessary to modify and use
15 * the m68k page table tree.
16 */
17
18#include <asm/virtconvert.h>
19
20/* Certain architectures need to do special things when pte's
21 * within a page table are directly modified. Thus, the following
22 * hook is made available.
23 */
24#define set_pte(pteptr, pteval) \
25 do{ \
26 *(pteptr) = (pteval); \
27 } while(0)
28#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
29
30
31/* PMD_SHIFT determines the size of the area a second-level page table can map */
32#ifdef CONFIG_SUN3
33#define PMD_SHIFT 17
34#else
35#define PMD_SHIFT 22
36#endif
37#define PMD_SIZE (1UL << PMD_SHIFT)
38#define PMD_MASK (~(PMD_SIZE-1))
39
40/* PGDIR_SHIFT determines what a third-level page table entry can map */
41#ifdef CONFIG_SUN3
42#define PGDIR_SHIFT 17
43#else
44#define PGDIR_SHIFT 25
45#endif
46#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
47#define PGDIR_MASK (~(PGDIR_SIZE-1))
48
49/*
50 * entries per page directory level: the m68k is configured as three-level,
51 * so we do have PMD level physically.
52 */
53#ifdef CONFIG_SUN3
54#define PTRS_PER_PTE 16
55#define PTRS_PER_PMD 1
56#define PTRS_PER_PGD 2048
57#else
58#define PTRS_PER_PTE 1024
59#define PTRS_PER_PMD 8
60#define PTRS_PER_PGD 128
61#endif
62#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
63#define FIRST_USER_ADDRESS 0
64
65/* Virtual address region for use by kernel_map() */
66#ifdef CONFIG_SUN3
67#define KMAP_START 0x0DC00000
68#define KMAP_END 0x0E000000
69#else
70#define KMAP_START 0xd0000000
71#define KMAP_END 0xf0000000
72#endif
73
74#ifndef CONFIG_SUN3
75/* Just any arbitrary offset to the start of the vmalloc VM area: the
76 * current 8MB value just means that there will be a 8MB "hole" after the
77 * physical memory until the kernel virtual memory starts. That means that
78 * any out-of-bounds memory accesses will hopefully be caught.
79 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
80 * area for the same reason. ;)
81 */
82#define VMALLOC_OFFSET (8*1024*1024)
83#define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
84#define VMALLOC_END KMAP_START
85#else
86extern unsigned long vmalloc_end;
87#define VMALLOC_START 0x0f800000
88#define VMALLOC_END vmalloc_end
89#endif /* CONFIG_SUN3 */
90
91/* zero page used for uninitialized stuff */
92extern void *empty_zero_page;
93
94/*
95 * ZERO_PAGE is a global shared page that is always zero: used
96 * for zero-mapped memory areas etc..
97 */
98#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
99
100/* number of bits that fit into a memory pointer */
101#define BITS_PER_PTR (8*sizeof(unsigned long))
102
103/* to align the pointer to a pointer address */
104#define PTR_MASK (~(sizeof(void*)-1))
105
106/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
107/* 64-bit machines, beware! SRB. */
108#define SIZEOF_PTR_LOG2 2
109
110extern void kernel_set_cachemode(void *addr, unsigned long size, int cmode);
111
112/*
113 * The m68k doesn't have any external MMU info: the kernel page
114 * tables contain all the necessary information. The Sun3 does, but
115 * they are updated on demand.
116 */
117static inline void update_mmu_cache(struct vm_area_struct *vma,
118 unsigned long address, pte_t pte)
119{
120}
121
122#endif /* !__ASSEMBLY__ */
123
124#define kern_addr_valid(addr) (1)
125
126#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
127 remap_pfn_range(vma, vaddr, pfn, size, prot)
128
129/* MMU-specific headers */
130
131#ifdef CONFIG_SUN3
132#include <asm/sun3_pgtable.h>
133#else
134#include <asm/motorola_pgtable.h>
135#endif
136
137#ifndef __ASSEMBLY__
138#include <asm-generic/pgtable.h>
139
140/*
141 * Macro to mark a page protection value as "uncacheable".
142 */
143#ifdef SUN3_PAGE_NOCACHE
144# define __SUN3_PAGE_NOCACHE SUN3_PAGE_NOCACHE
145#else
146# define __SUN3_PAGE_NOCACHE 0
147#endif
148#define pgprot_noncached(prot) \
149 (MMU_IS_SUN3 \
150 ? (__pgprot(pgprot_val(prot) | __SUN3_PAGE_NOCACHE)) \
151 : ((MMU_IS_851 || MMU_IS_030) \
152 ? (__pgprot(pgprot_val(prot) | _PAGE_NOCACHE030)) \
153 : (MMU_IS_040 || MMU_IS_060) \
154 ? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S)) \
155 : (prot)))
156
157#endif /* !__ASSEMBLY__ */
158
159/*
160 * No page table caches to initialise
161 */
162#define pgtable_cache_init() do { } while (0)
163
164#define check_pgt_cache() do { } while (0)
165
166#endif /* _M68K_PGTABLE_H */
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