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-rw-r--r--include/asm-m32r/cacheflush.h3
-rw-r--r--include/asm-m32r/ide.h3
-rw-r--r--include/asm-m32r/m32102.h7
-rw-r--r--include/asm-m32r/ptrace.h28
-rw-r--r--include/asm-m32r/sigcontext.h13
-rw-r--r--include/asm-m32r/termbits.h11
6 files changed, 26 insertions, 39 deletions
diff --git a/include/asm-m32r/cacheflush.h b/include/asm-m32r/cacheflush.h
index 8b261b49149e..56961a9511b2 100644
--- a/include/asm-m32r/cacheflush.h
+++ b/include/asm-m32r/cacheflush.h
@@ -9,6 +9,7 @@ extern void _flush_cache_copyback_all(void);
9#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104) 9#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
10#define flush_cache_all() do { } while (0) 10#define flush_cache_all() do { } while (0)
11#define flush_cache_mm(mm) do { } while (0) 11#define flush_cache_mm(mm) do { } while (0)
12#define flush_cache_dup_mm(mm) do { } while (0)
12#define flush_cache_range(vma, start, end) do { } while (0) 13#define flush_cache_range(vma, start, end) do { } while (0)
13#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) 14#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
14#define flush_dcache_page(page) do { } while (0) 15#define flush_dcache_page(page) do { } while (0)
@@ -29,6 +30,7 @@ extern void smp_flush_cache_all(void);
29#elif defined(CONFIG_CHIP_M32102) 30#elif defined(CONFIG_CHIP_M32102)
30#define flush_cache_all() do { } while (0) 31#define flush_cache_all() do { } while (0)
31#define flush_cache_mm(mm) do { } while (0) 32#define flush_cache_mm(mm) do { } while (0)
33#define flush_cache_dup_mm(mm) do { } while (0)
32#define flush_cache_range(vma, start, end) do { } while (0) 34#define flush_cache_range(vma, start, end) do { } while (0)
33#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) 35#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
34#define flush_dcache_page(page) do { } while (0) 36#define flush_dcache_page(page) do { } while (0)
@@ -41,6 +43,7 @@ extern void smp_flush_cache_all(void);
41#else 43#else
42#define flush_cache_all() do { } while (0) 44#define flush_cache_all() do { } while (0)
43#define flush_cache_mm(mm) do { } while (0) 45#define flush_cache_mm(mm) do { } while (0)
46#define flush_cache_dup_mm(mm) do { } while (0)
44#define flush_cache_range(vma, start, end) do { } while (0) 47#define flush_cache_range(vma, start, end) do { } while (0)
45#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) 48#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
46#define flush_dcache_page(page) do { } while (0) 49#define flush_dcache_page(page) do { } while (0)
diff --git a/include/asm-m32r/ide.h b/include/asm-m32r/ide.h
index 219a0f74eff3..c82ebe8f250d 100644
--- a/include/asm-m32r/ide.h
+++ b/include/asm-m32r/ide.h
@@ -32,7 +32,8 @@
32static __inline__ int ide_default_irq(unsigned long base) 32static __inline__ int ide_default_irq(unsigned long base)
33{ 33{
34 switch (base) { 34 switch (base) {
35#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2) 35#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2) \
36 || defined(CONFIG_PLAT_OPSPUT)
36 case 0x1f0: return PLD_IRQ_CFIREQ; 37 case 0x1f0: return PLD_IRQ_CFIREQ;
37 default: 38 default:
38 return 0; 39 return 0;
diff --git a/include/asm-m32r/m32102.h b/include/asm-m32r/m32102.h
index a1f0d1fe9eb8..52807f8db166 100644
--- a/include/asm-m32r/m32102.h
+++ b/include/asm-m32r/m32102.h
@@ -104,7 +104,8 @@
104#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */ 104#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
105#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */ 105#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
106 106
107#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32104) 107#if (defined(CONFIG_CHIP_M32700) && !defined(CONFIG_PLAT_MAPPI2)) \
108 || defined(CONFIG_CHIP_M32104)
108#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */ 109#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */
109#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */ 110#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */
110#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */ 111#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */
@@ -117,7 +118,7 @@
117#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */ 118#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */
118#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */ 119#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */
119#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */ 120#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */
120#else /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */ 121#else
121#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */ 122#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */
122#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */ 123#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */
123#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */ 124#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */
@@ -130,7 +131,7 @@
130#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */ 131#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */
131#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */ 132#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */
132#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */ 133#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */
133#endif /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */ 134#endif
134 135
135#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */ 136#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */
136#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */ 137#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */
diff --git a/include/asm-m32r/ptrace.h b/include/asm-m32r/ptrace.h
index 2d2a6c97331e..632b4ce4269a 100644
--- a/include/asm-m32r/ptrace.h
+++ b/include/asm-m32r/ptrace.h
@@ -33,21 +33,10 @@
33#define PT_R15 PT_SP 33#define PT_R15 PT_SP
34 34
35/* processor status and miscellaneous context registers. */ 35/* processor status and miscellaneous context registers. */
36#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
37#define PT_ACC0H 15 36#define PT_ACC0H 15
38#define PT_ACC0L 16 37#define PT_ACC0L 16
39#define PT_ACC1H 17 38#define PT_ACC1H 17 /* ISA_DSP_LEVEL2 only */
40#define PT_ACC1L 18 39#define PT_ACC1L 18 /* ISA_DSP_LEVEL2 only */
41#define PT_ACCH PT_ACC0H
42#define PT_ACCL PT_ACC0L
43#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
44#define PT_ACCH 15
45#define PT_ACCL 16
46#define PT_DUMMY_ACC1H 17
47#define PT_DUMMY_ACC1L 18
48#else
49#error unknown isa conifiguration
50#endif
51#define PT_PSW 19 40#define PT_PSW 19
52#define PT_BPC 20 41#define PT_BPC 20
53#define PT_BBPSW 21 42#define PT_BBPSW 21
@@ -103,19 +92,10 @@ struct pt_regs {
103 long syscall_nr; 92 long syscall_nr;
104 93
105 /* Saved main processor status and miscellaneous context registers. */ 94 /* Saved main processor status and miscellaneous context registers. */
106#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
107 unsigned long acc0h; 95 unsigned long acc0h;
108 unsigned long acc0l; 96 unsigned long acc0l;
109 unsigned long acc1h; 97 unsigned long acc1h; /* ISA_DSP_LEVEL2 only */
110 unsigned long acc1l; 98 unsigned long acc1l; /* ISA_DSP_LEVEL2 only */
111#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
112 unsigned long acch;
113 unsigned long accl;
114 unsigned long dummy_acc1h;
115 unsigned long dummy_acc1l;
116#else
117#error unknown isa configuration
118#endif
119 unsigned long psw; 99 unsigned long psw;
120 unsigned long bpc; /* saved PC for TRAP syscalls */ 100 unsigned long bpc; /* saved PC for TRAP syscalls */
121 unsigned long bbpsw; 101 unsigned long bbpsw;
diff --git a/include/asm-m32r/sigcontext.h b/include/asm-m32r/sigcontext.h
index 73025c0c41a1..62537dc4dec9 100644
--- a/include/asm-m32r/sigcontext.h
+++ b/include/asm-m32r/sigcontext.h
@@ -23,19 +23,10 @@ struct sigcontext {
23 unsigned long sc_r12; 23 unsigned long sc_r12;
24 24
25 /* Saved main processor status and miscellaneous context registers. */ 25 /* Saved main processor status and miscellaneous context registers. */
26#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
27 unsigned long sc_acc0h; 26 unsigned long sc_acc0h;
28 unsigned long sc_acc0l; 27 unsigned long sc_acc0l;
29 unsigned long sc_acc1h; 28 unsigned long sc_acc1h; /* ISA_DSP_LEVEL2 only */
30 unsigned long sc_acc1l; 29 unsigned long sc_acc1l; /* ISA_DSP_LEVEL2 only */
31#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
32 unsigned long sc_acch;
33 unsigned long sc_accl;
34 unsigned long sc_dummy_acc1h;
35 unsigned long sc_dummy_acc1l;
36#else
37#error unknown isa configuration
38#endif
39 unsigned long sc_psw; 30 unsigned long sc_psw;
40 unsigned long sc_bpc; /* saved PC for TRAP syscalls */ 31 unsigned long sc_bpc; /* saved PC for TRAP syscalls */
41 unsigned long sc_bbpsw; 32 unsigned long sc_bbpsw;
diff --git a/include/asm-m32r/termbits.h b/include/asm-m32r/termbits.h
index 5ace3702df75..faf2bd0504c1 100644
--- a/include/asm-m32r/termbits.h
+++ b/include/asm-m32r/termbits.h
@@ -19,6 +19,17 @@ struct termios {
19 cc_t c_cc[NCCS]; /* control characters */ 19 cc_t c_cc[NCCS]; /* control characters */
20}; 20};
21 21
22struct ktermios {
23 tcflag_t c_iflag; /* input mode flags */
24 tcflag_t c_oflag; /* output mode flags */
25 tcflag_t c_cflag; /* control mode flags */
26 tcflag_t c_lflag; /* local mode flags */
27 cc_t c_line; /* line discipline */
28 cc_t c_cc[NCCS]; /* control characters */
29 speed_t c_ispeed; /* input speed */
30 speed_t c_ospeed; /* output speed */
31};
32
22/* c_cc characters */ 33/* c_cc characters */
23#define VINTR 0 34#define VINTR 0
24#define VQUIT 1 35#define VQUIT 1