diff options
Diffstat (limited to 'include/asm-m32r')
-rw-r--r-- | include/asm-m32r/m32102peri.h | 468 | ||||
-rw-r--r-- | include/asm-m32r/m32r.h | 1 |
2 files changed, 0 insertions, 469 deletions
diff --git a/include/asm-m32r/m32102peri.h b/include/asm-m32r/m32102peri.h deleted file mode 100644 index 3c12955ad0f0..000000000000 --- a/include/asm-m32r/m32102peri.h +++ /dev/null | |||
@@ -1,468 +0,0 @@ | |||
1 | /* $Id$ | ||
2 | * | ||
3 | * This file is subject to the terms and conditions of the GNU General Public | ||
4 | * License. See the file "COPYING" in the main directory of this archive | ||
5 | * for more details. | ||
6 | * | ||
7 | * Copyright (C) 2000,2001 by Hiroyuki Kondo | ||
8 | */ | ||
9 | |||
10 | #ifndef __ASSEMBLY__ | ||
11 | |||
12 | typedef void V; | ||
13 | typedef char B; | ||
14 | typedef short S; | ||
15 | typedef int W; | ||
16 | typedef long L; | ||
17 | typedef float F; | ||
18 | typedef double D; | ||
19 | typedef unsigned char UB; | ||
20 | typedef unsigned short US; | ||
21 | typedef unsigned int UW; | ||
22 | typedef unsigned long UL; | ||
23 | typedef const unsigned int CUW; | ||
24 | |||
25 | /********************************* | ||
26 | |||
27 | M32102 ICU | ||
28 | |||
29 | *********************************/ | ||
30 | #define ICUISTS (UW *)0xa0EFF004 | ||
31 | #define ICUIREQ0 (UW *)0xa0EFF008 | ||
32 | #define ICUIREQ1 (UW *)0xa0EFF00C | ||
33 | |||
34 | #define ICUSBICR (UW *)0xa0EFF018 | ||
35 | #define ICUIMASK (UW *)0xa0EFF01C | ||
36 | |||
37 | #define ICUCR1 (UW *)0xa0EFF200 /* INT0 */ | ||
38 | #define ICUCR2 (UW *)0xa0EFF204 /* INT1 */ | ||
39 | #define ICUCR3 (UW *)0xa0EFF208 /* INT2 */ | ||
40 | #define ICUCR4 (UW *)0xa0EFF20C /* INT3 */ | ||
41 | #define ICUCR5 (UW *)0xa0EFF210 /* INT4 */ | ||
42 | #define ICUCR6 (UW *)0xa0EFF214 /* INT5 */ | ||
43 | #define ICUCR7 (UW *)0xa0EFF218 /* INT6 */ | ||
44 | |||
45 | #define ICUCR16 (UW *)0xa0EFF23C /* MFT0 */ | ||
46 | #define ICUCR17 (UW *)0xa0EFF240 /* MFT1 */ | ||
47 | #define ICUCR18 (UW *)0xa0EFF244 /* MFT2 */ | ||
48 | #define ICUCR19 (UW *)0xa0EFF248 /* MFT3 */ | ||
49 | #define ICUCR20 (UW *)0xa0EFF24C /* MFT4 */ | ||
50 | #define ICUCR21 (UW *)0xa0EFF250 /* MFT5 */ | ||
51 | |||
52 | #define ICUCR32 (UW *)0xa0EFF27C /* DMA0 */ | ||
53 | #define ICUCR33 (UW *)0xa0EFF280 /* DMA1 */ | ||
54 | |||
55 | #define ICUCR48 (UW *)0xa0EFF2BC /* SIO0R */ | ||
56 | #define ICUCR49 (UW *)0xa0EFF2C0 /* SIO0S */ | ||
57 | #define ICUCR50 (UW *)0xa0EFF2C4 /* SIO1R */ | ||
58 | #define ICUCR51 (UW *)0xa0EFF2C8 /* SIO1S */ | ||
59 | #define ICUCR52 (UW *)0xa0EFF2CC /* SIO2R */ | ||
60 | #define ICUCR53 (UW *)0xa0EFF2D0 /* SIO2S */ | ||
61 | #define ICUCR54 (UW *)0xa0EFF2D4 /* SIO3R */ | ||
62 | #define ICUCR55 (UW *)0xa0EFF2D8 /* SIO3S */ | ||
63 | #define ICUCR56 (UW *)0xa0EFF2DC /* SIO4R */ | ||
64 | #define ICUCR57 (UW *)0xa0EFF2E0 /* SIO4S */ | ||
65 | |||
66 | /********************************* | ||
67 | |||
68 | M32102 MFT | ||
69 | |||
70 | *********************************/ | ||
71 | #define MFTCR (US *)0xa0EFC002 | ||
72 | #define MFTRPR (UB *)0xa0EFC006 | ||
73 | |||
74 | #define MFT0MOD (US *)0xa0EFC102 | ||
75 | #define MFT0BOS (US *)0xa0EFC106 | ||
76 | #define MFT0CUT (US *)0xa0EFC10A | ||
77 | #define MFT0RLD (US *)0xa0EFC10E | ||
78 | #define MFT0CRLD (US *)0xa0EFC112 | ||
79 | |||
80 | #define MFT1MOD (US *)0xa0EFC202 | ||
81 | #define MFT1BOS (US *)0xa0EFC206 | ||
82 | #define MFT1CUT (US *)0xa0EFC20A | ||
83 | #define MFT1RLD (US *)0xa0EFC20E | ||
84 | #define MFT1CRLD (US *)0xa0EFC212 | ||
85 | |||
86 | #define MFT2MOD (US *)0xa0EFC302 | ||
87 | #define MFT2BOS (US *)0xa0EFC306 | ||
88 | #define MFT2CUT (US *)0xa0EFC30A | ||
89 | #define MFT2RLD (US *)0xa0EFC30E | ||
90 | #define MFT2CRLD (US *)0xa0EFC312 | ||
91 | |||
92 | #define MFT3MOD (US *)0xa0EFC402 | ||
93 | #define MFT3CUT (US *)0xa0EFC40A | ||
94 | #define MFT3RLD (US *)0xa0EFC40E | ||
95 | #define MFT3CRLD (US *)0xa0EFC412 | ||
96 | |||
97 | #define MFT4MOD (US *)0xa0EFC502 | ||
98 | #define MFT4CUT (US *)0xa0EFC50A | ||
99 | #define MFT4RLD (US *)0xa0EFC50E | ||
100 | #define MFT4CRLD (US *)0xa0EFC512 | ||
101 | |||
102 | #define MFT5MOD (US *)0xa0EFC602 | ||
103 | #define MFT5CUT (US *)0xa0EFC60A | ||
104 | #define MFT5RLD (US *)0xa0EFC60E | ||
105 | #define MFT5CRLD (US *)0xa0EFC612 | ||
106 | |||
107 | /********************************* | ||
108 | |||
109 | M32102 SIO | ||
110 | |||
111 | *********************************/ | ||
112 | |||
113 | #define SIO0CR (volatile int *)0xa0efd000 | ||
114 | #define SIO0MOD0 (volatile int *)0xa0efd004 | ||
115 | #define SIO0MOD1 (volatile int *)0xa0efd008 | ||
116 | #define SIO0STS (volatile int *)0xa0efd00c | ||
117 | #define SIO0IMASK (volatile int *)0xa0efd010 | ||
118 | #define SIO0BAUR (volatile int *)0xa0efd014 | ||
119 | #define SIO0RBAUR (volatile int *)0xa0efd018 | ||
120 | #define SIO0TXB (volatile int *)0xa0efd01c | ||
121 | #define SIO0RXB (volatile int *)0xa0efd020 | ||
122 | |||
123 | #define SIO1CR (volatile int *)0xa0efd100 | ||
124 | #define SIO1MOD0 (volatile int *)0xa0efd104 | ||
125 | #define SIO1MOD1 (volatile int *)0xa0efd108 | ||
126 | #define SIO1STS (volatile int *)0xa0efd10c | ||
127 | #define SIO1IMASK (volatile int *)0xa0efd110 | ||
128 | #define SIO1BAUR (volatile int *)0xa0efd114 | ||
129 | #define SIO1RBAUR (volatile int *)0xa0efd118 | ||
130 | #define SIO1TXB (volatile int *)0xa0efd11c | ||
131 | #define SIO1RXB (volatile int *)0xa0efd120 | ||
132 | /********************************* | ||
133 | |||
134 | M32102 PORT | ||
135 | |||
136 | *********************************/ | ||
137 | #define PIEN (UB *)0xa0EF1003 /* input enable */ | ||
138 | |||
139 | #define P0DATA (UB *)0xa0EF1020 /* data */ | ||
140 | #define P1DATA (UB *)0xa0EF1021 | ||
141 | #define P2DATA (UB *)0xa0EF1022 | ||
142 | #define P3DATA (UB *)0xa0EF1023 | ||
143 | #define P4DATA (UB *)0xa0EF1024 | ||
144 | #define P5DATA (UB *)0xa0EF1025 | ||
145 | #define P6DATA (UB *)0xa0EF1026 | ||
146 | #define P7DATA (UB *)0xa0EF1027 | ||
147 | |||
148 | #define P0DIR (UB *)0xa0EF1040 /* direction */ | ||
149 | #define P1DIR (UB *)0xa0EF1041 | ||
150 | #define P2DIR (UB *)0xa0EF1042 | ||
151 | #define P3DIR (UB *)0xa0EF1043 | ||
152 | #define P4DIR (UB *)0xa0EF1044 | ||
153 | #define P5DIR (UB *)0xa0EF1045 | ||
154 | #define P6DIR (UB *)0xa0EF1046 | ||
155 | #define P7DIR (UB *)0xa0EF1047 | ||
156 | |||
157 | #define P0MOD (US *)0xa0EF1060 /* mode control */ | ||
158 | #define P1MOD (US *)0xa0EF1062 | ||
159 | #define P2MOD (US *)0xa0EF1064 | ||
160 | #define P3MOD (US *)0xa0EF1066 | ||
161 | #define P4MOD (US *)0xa0EF1068 | ||
162 | #define P5MOD (US *)0xa0EF106A | ||
163 | #define P6MOD (US *)0xa0EF106C | ||
164 | #define P7MOD (US *)0xa0EF106E | ||
165 | |||
166 | #define P0ODCR (UB *)0xa0EF1080 /* open-drain control */ | ||
167 | #define P1ODCR (UB *)0xa0EF1081 | ||
168 | #define P2ODCR (UB *)0xa0EF1082 | ||
169 | #define P3ODCR (UB *)0xa0EF1083 | ||
170 | #define P4ODCR (UB *)0xa0EF1084 | ||
171 | #define P5ODCR (UB *)0xa0EF1085 | ||
172 | #define P6ODCR (UB *)0xa0EF1086 | ||
173 | #define P7ODCR (UB *)0xa0EF1087 | ||
174 | |||
175 | /********************************* | ||
176 | |||
177 | M32102 Cache | ||
178 | |||
179 | ********************************/ | ||
180 | |||
181 | #define MCCR (US *)0xFFFFFFFE | ||
182 | |||
183 | |||
184 | #else /* __ASSEMBLY__ */ | ||
185 | |||
186 | ;; | ||
187 | ;; PIO 0x80ef1000 | ||
188 | ;; | ||
189 | |||
190 | #define PIEN 0xa0ef1000 | ||
191 | |||
192 | #define P0DATA 0xa0ef1020 | ||
193 | #define P1DATA 0xa0ef1021 | ||
194 | #define P2DATA 0xa0ef1022 | ||
195 | #define P3DATA 0xa0ef1023 | ||
196 | #define P4DATA 0xa0ef1024 | ||
197 | #define P5DATA 0xa0ef1025 | ||
198 | #define P6DATA 0xa0ef1026 | ||
199 | #define P7DATA 0xa0ef1027 | ||
200 | |||
201 | #define P0DIR 0xa0ef1040 | ||
202 | #define P1DIR 0xa0ef1041 | ||
203 | #define P2DIR 0xa0ef1042 | ||
204 | #define P3DIR 0xa0ef1043 | ||
205 | #define P4DIR 0xa0ef1044 | ||
206 | #define P5DIR 0xa0ef1045 | ||
207 | #define P6DIR 0xa0ef1046 | ||
208 | #define P7DIR 0xa0ef1047 | ||
209 | |||
210 | #define P0MOD 0xa0ef1060 | ||
211 | #define P1MOD 0xa0ef1062 | ||
212 | #define P2MOD 0xa0ef1064 | ||
213 | #define P3MOD 0xa0ef1066 | ||
214 | #define P4MOD 0xa0ef1068 | ||
215 | #define P5MOD 0xa0ef106a | ||
216 | #define P6MOD 0xa0ef106c | ||
217 | #define P7MOD 0xa0ef106e | ||
218 | ; | ||
219 | #define P0ODCR 0xa0ef1080 | ||
220 | #define P1ODCR 0xa0ef1081 | ||
221 | #define P2ODCR 0xa0ef1082 | ||
222 | #define P3ODCR 0xa0ef1083 | ||
223 | #define P4ODCR 0xa0ef1084 | ||
224 | #define P5ODCR 0xa0ef1085 | ||
225 | #define P6ODCR 0xa0ef1086 | ||
226 | #define P7ODCR 0xa0ef1087 | ||
227 | |||
228 | ;; | ||
229 | ;; WDT 0xa0ef2000 | ||
230 | ;; | ||
231 | |||
232 | #define WDTCR 0xa0ef2000 | ||
233 | |||
234 | |||
235 | ;; | ||
236 | ;; CLK 0xa0ef4000 | ||
237 | ;; | ||
238 | |||
239 | #define CPUCLKCR 0xa0ef4000 | ||
240 | #define CLKMOD 0xa0ef4004 | ||
241 | #define PLLCR 0xa0ef4008 | ||
242 | |||
243 | |||
244 | ;; | ||
245 | ;; BSEL 0xa0ef5000 | ||
246 | ;; | ||
247 | |||
248 | #define BSEL0CR 0xa0ef5000 | ||
249 | #define BSEL1CR 0xa0ef5004 | ||
250 | #define BSEL2CR 0xa0ef5008 | ||
251 | #define BSEL3CR 0xa0ef500c | ||
252 | #define BSEL4CR 0xa0ef5010 | ||
253 | #define BSEL5CR 0xa0ef5014 | ||
254 | |||
255 | |||
256 | ;; | ||
257 | ;; SDRAMC 0xa0ef6000 | ||
258 | ;; | ||
259 | |||
260 | #define SDRF0 0xa0ef6000 | ||
261 | #define SDRF1 0xa0ef6004 | ||
262 | #define SDIR0 0xa0ef6008 | ||
263 | #define SDIR1 0xa0ef600c | ||
264 | #define SDBR 0xa0ef6010 | ||
265 | |||
266 | ;; CH0 | ||
267 | #define SD0ADR 0xa0ef6020 | ||
268 | #define SD0SZ 0xa0ef6022 | ||
269 | #define SD0ER 0xa0ef6024 | ||
270 | #define SD0TR 0xa0ef6028 | ||
271 | #define SD0MOD 0xa0ef602c | ||
272 | |||
273 | ;; CH1 | ||
274 | #define SD1ADR 0xa0ef6040 | ||
275 | #define SD1SZ 0xa0ef6042 | ||
276 | #define SD1ER 0xa0ef6044 | ||
277 | #define SD1TR 0xa0ef6048 | ||
278 | #define SD1MOD 0xa0ef604c | ||
279 | |||
280 | |||
281 | ;; | ||
282 | ;; DMAC 0xa0ef8000 | ||
283 | ;; | ||
284 | |||
285 | #define DMAEN 0xa0ef8000 | ||
286 | #define DMAISTS 0xa0ef8004 | ||
287 | #define DMAEDET 0xa0ef8008 | ||
288 | #define DMAASTS 0xa0ef800c | ||
289 | |||
290 | ;; CH0 | ||
291 | #define DMA0CR0 0xa0ef8100 | ||
292 | #define DMA0CR1 0xa0ef8104 | ||
293 | #define DMA0CSA 0xa0ef8108 | ||
294 | #define DMA0RSA 0xa0ef810c | ||
295 | #define DMA0CDA 0xa0ef8110 | ||
296 | #define DMA0RDA 0xa0ef8114 | ||
297 | #define DMA0CBCUT 0xa0ef8118 | ||
298 | #define DMA0RBCUT 0xa0ef811c | ||
299 | |||
300 | ;; CH1 | ||
301 | #define DMA1CR0 0xa0ef8200 | ||
302 | #define DMA1CR1 0xa0ef8204 | ||
303 | #define DMA1CSA 0xa0ef8208 | ||
304 | #define DMA1RSA 0xa0ef820c | ||
305 | #define DMA1CDA 0xa0ef8210 | ||
306 | #define DMA1RDA 0xa0ef8214 | ||
307 | #define DMA1CBCUT 0xa0ef8218 | ||
308 | #define DMA1RBCUT 0xa0ef821c | ||
309 | |||
310 | |||
311 | ;; | ||
312 | ;; MFT 0xa0efc000 | ||
313 | ;; | ||
314 | |||
315 | #define MFTCR 0xa0efc000 | ||
316 | #define MFTRPR 0xa0efc004 | ||
317 | |||
318 | ;; CH0 | ||
319 | #define MFT0MOD 0xa0efc100 | ||
320 | #define MFT0BOS 0xa0efc104 | ||
321 | #define MFT0CUT 0xa0efc108 | ||
322 | #define MFT0RLD 0xa0efc10c | ||
323 | #define MFT0CMPRLD 0xa0efc110 | ||
324 | |||
325 | ;; CH1 | ||
326 | #define MFT1MOD 0xa0efc200 | ||
327 | #define MFT1BOS 0xa0efc204 | ||
328 | #define MFT1CUT 0xa0efc208 | ||
329 | #define MFT1RLD 0xa0efc20c | ||
330 | #define MFT1CMPRLD 0xa0efc210 | ||
331 | |||
332 | ;; CH2 | ||
333 | #define MFT2MOD 0xa0efc300 | ||
334 | #define MFT2BOS 0xa0efc304 | ||
335 | #define MFT2CUT 0xa0efc308 | ||
336 | #define MFT2RLD 0xa0efc30c | ||
337 | #define MFT2CMPRLD 0xa0efc310 | ||
338 | |||
339 | ;; CH3 | ||
340 | #define MFT3MOD 0xa0efc400 | ||
341 | #define MFT3BOS 0xa0efc404 | ||
342 | #define MFT3CUT 0xa0efc408 | ||
343 | #define MFT3RLD 0xa0efc40c | ||
344 | #define MFT3CMPRLD 0xa0efc410 | ||
345 | |||
346 | ;; CH4 | ||
347 | #define MFT4MOD 0xa0efc500 | ||
348 | #define MFT4BOS 0xa0efc504 | ||
349 | #define MFT4CUT 0xa0efc508 | ||
350 | #define MFT4RLD 0xa0efc50c | ||
351 | #define MFT4CMPRLD 0xa0efc510 | ||
352 | |||
353 | ;; CH5 | ||
354 | #define MFT5MOD 0xa0efc600 | ||
355 | #define MFT5BOS 0xa0efc604 | ||
356 | #define MFT5CUT 0xa0efc608 | ||
357 | #define MFT5RLD 0xa0efc60c | ||
358 | #define MFT5CMPRLD 0xa0efc610 | ||
359 | |||
360 | |||
361 | ;; | ||
362 | ;; SIO 0xa0efd000 | ||
363 | ;; | ||
364 | |||
365 | ;; CH0 | ||
366 | #define SIO0CR 0xa0efd000 | ||
367 | #define SIO0MOD0 0xa0efd004 | ||
368 | #define SIO0MOD1 0xa0efd008 | ||
369 | #define SIO0STS 0xa0efd00c | ||
370 | #define SIO0IMASK 0xa0efd010 | ||
371 | #define SIO0BAUR 0xa0efd014 | ||
372 | #define SIO0RBAUR 0xa0efd018 | ||
373 | #define SIO0TXB 0xa0efd01c | ||
374 | #define SIO0RXB 0xa0efd020 | ||
375 | |||
376 | ;; CH1 | ||
377 | #define SIO1CR 0xa0efd100 | ||
378 | #define SIO1MOD0 0xa0efd104 | ||
379 | #define SIO1MOD1 0xa0efd108 | ||
380 | #define SIO1STS 0xa0efd10c | ||
381 | #define SIO1IMASK 0xa0efd110 | ||
382 | #define SIO1BAUR 0xa0efd114 | ||
383 | #define SIO1RBAUR 0xa0efd118 | ||
384 | #define SIO1TXB 0xa0efd11c | ||
385 | #define SIO1RXB 0xa0efd120 | ||
386 | |||
387 | ;; CH2 | ||
388 | #define SIO2CR 0xa0efd200 | ||
389 | #define SIO2MOD0 0xa0efd204 | ||
390 | #define SIO2MOD1 0xa0efd208 | ||
391 | #define SIO2STS 0xa0efd20c | ||
392 | #define SIO2IMASK 0xa0efd210 | ||
393 | #define SIO2BAUR 0xa0efd214 | ||
394 | #define SIO2RBAUR 0xa0efd218 | ||
395 | #define SIO2TXB 0xa0efd21c | ||
396 | #define SIO2RXB 0xa0efd220 | ||
397 | |||
398 | ;; CH3 | ||
399 | #define SIO3CR 0xa0efd300 | ||
400 | #define SIO3MOD0 0xa0efd304 | ||
401 | #define SIO3MOD1 0xa0efd308 | ||
402 | #define SIO3STS 0xa0efd30c | ||
403 | #define SIO3IMASK 0xa0efd310 | ||
404 | #define SIO3BAUR 0xa0efd314 | ||
405 | #define SIO3RBAUR 0xa0efd318 | ||
406 | #define SIO3TXB 0xa0efd31c | ||
407 | #define SIO3RXB 0xa0efd320 | ||
408 | |||
409 | ;; CH4 | ||
410 | #define SIO4CR 0xa0efd400 | ||
411 | #define SIO4MOD0 0xa0efd404 | ||
412 | #define SIO4MOD1 0xa0efd408 | ||
413 | #define SIO4STS 0xa0efd40c | ||
414 | #define SIO4IMASK 0xa0efd410 | ||
415 | #define SIO4BAUR 0xa0efd414 | ||
416 | #define SIO4RBAUR 0xa0efd418 | ||
417 | #define SIO4TXB 0xa0efd41c | ||
418 | #define SIO4RXB 0xa0efd420 | ||
419 | |||
420 | |||
421 | ;; | ||
422 | ;; ICU 0xa0eff000 | ||
423 | ;; | ||
424 | |||
425 | #define ICUISTS 0xa0eff004 | ||
426 | #define ICUIREQ0 0xa0eff008 | ||
427 | #define ICUIREQ1 0xa0eff00c | ||
428 | |||
429 | #define ICUSBICR 0xa0eff018 | ||
430 | #define ICUIMASK 0xa0eff01c | ||
431 | |||
432 | #define ICUCR1 0xa0eff200 | ||
433 | #define ICUCR2 0xa0eff204 | ||
434 | #define ICUCR3 0xa0eff208 | ||
435 | #define ICUCR4 0xa0eff20c | ||
436 | #define ICUCR5 0xa0eff210 | ||
437 | #define ICUCR6 0xa0eff214 | ||
438 | #define ICUCR7 0xa0eff218 | ||
439 | |||
440 | #define ICUCR16 0xa0eff23c | ||
441 | #define ICUCR17 0xa0eff240 | ||
442 | #define ICUCR18 0xa0eff244 | ||
443 | #define ICUCR19 0xa0eff248 | ||
444 | #define ICUCR20 0xa0eff24c | ||
445 | #define ICUCR21 0xa0eff250 | ||
446 | |||
447 | #define ICUCR32 0xa0eff27c | ||
448 | #define ICUCR33 0xa0eff280 | ||
449 | |||
450 | #define ICUCR48 0xa0eff2bc | ||
451 | #define ICUCR49 0xa0eff2c0 | ||
452 | #define ICUCR50 0xa0eff2c4 | ||
453 | #define ICUCR51 0xa0eff2c8 | ||
454 | #define ICUCR52 0xa0eff2cc | ||
455 | #define ICUCR53 0xa0eff2d0 | ||
456 | #define ICUCR54 0xa0eff2d4 | ||
457 | #define ICUCR55 0xa0eff2d8 | ||
458 | #define ICUCR56 0xa0eff2dc | ||
459 | #define ICUCR57 0xa0eff2e0 | ||
460 | |||
461 | ;; | ||
462 | ;; CACHE | ||
463 | ;; | ||
464 | |||
465 | #define MCCR 0xfffffffc | ||
466 | |||
467 | |||
468 | #endif /* __ASSEMBLY__ */ | ||
diff --git a/include/asm-m32r/m32r.h b/include/asm-m32r/m32r.h index fd2b2823762b..ec142be00862 100644 --- a/include/asm-m32r/m32r.h +++ b/include/asm-m32r/m32r.h | |||
@@ -16,7 +16,6 @@ | |||
16 | || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \ | 16 | || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \ |
17 | || defined(CONFIG_CHIP_OPSP) | 17 | || defined(CONFIG_CHIP_OPSP) |
18 | #include <asm/m32102.h> | 18 | #include <asm/m32102.h> |
19 | #include <asm/m32102peri.h> | ||
20 | #endif | 19 | #endif |
21 | 20 | ||
22 | /* Platform type */ | 21 | /* Platform type */ |