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-rw-r--r--include/asm-m32r/assembler.h10
-rw-r--r--include/asm-m32r/atomic.h1
-rw-r--r--include/asm-m32r/cacheflush.h2
-rw-r--r--include/asm-m32r/irq.h16
-rw-r--r--include/asm-m32r/m32102.h38
-rw-r--r--include/asm-m32r/m32104ut/m32104ut_pld.h163
-rw-r--r--include/asm-m32r/m32r.h8
-rw-r--r--include/asm-m32r/mman.h1
-rw-r--r--include/asm-m32r/system.h12
-rw-r--r--include/asm-m32r/unistd.h12
10 files changed, 233 insertions, 30 deletions
diff --git a/include/asm-m32r/assembler.h b/include/asm-m32r/assembler.h
index e1dff9d6baad..b7f4d8aaeb46 100644
--- a/include/asm-m32r/assembler.h
+++ b/include/asm-m32r/assembler.h
@@ -52,7 +52,7 @@
52 or3 \reg, \reg, #low(\x) 52 or3 \reg, \reg, #low(\x)
53 .endm 53 .endm
54 54
55#if !defined(CONFIG_CHIP_M32102) 55#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
56#define STI(reg) STI_M reg 56#define STI(reg) STI_M reg
57 .macro STI_M reg 57 .macro STI_M reg
58 setpsw #0x40 -> nop 58 setpsw #0x40 -> nop
@@ -64,7 +64,7 @@
64 clrpsw #0x40 -> nop 64 clrpsw #0x40 -> nop
65 ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1). 65 ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
66 .endm 66 .endm
67#else /* CONFIG_CHIP_M32102 */ 67#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
68#define STI(reg) STI_M reg 68#define STI(reg) STI_M reg
69 .macro STI_M reg 69 .macro STI_M reg
70 mvfc \reg, psw 70 mvfc \reg, psw
@@ -191,12 +191,12 @@
191 and \reg, sp 191 and \reg, sp
192 .endm 192 .endm
193 193
194#if !defined(CONFIG_CHIP_M32102) 194#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
195 .macro SWITCH_TO_KERNEL_STACK 195 .macro SWITCH_TO_KERNEL_STACK
196 ; switch to kernel stack (spi) 196 ; switch to kernel stack (spi)
197 clrpsw #0x80 -> nop 197 clrpsw #0x80 -> nop
198 .endm 198 .endm
199#else /* CONFIG_CHIP_M32102 */ 199#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
200 .macro SWITCH_TO_KERNEL_STACK 200 .macro SWITCH_TO_KERNEL_STACK
201 push r0 ; save r0 for working 201 push r0 ; save r0 for working
202 mvfc r0, psw 202 mvfc r0, psw
@@ -218,7 +218,7 @@
218 .fillinsn 218 .fillinsn
2192: 2192:
220 .endm 220 .endm
221#endif /* CONFIG_CHIP_M32102 */ 221#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
222 222
223#endif /* __ASSEMBLY__ */ 223#endif /* __ASSEMBLY__ */
224 224
diff --git a/include/asm-m32r/atomic.h b/include/asm-m32r/atomic.h
index ef1fb8ea4726..70761278b6cb 100644
--- a/include/asm-m32r/atomic.h
+++ b/include/asm-m32r/atomic.h
@@ -313,4 +313,5 @@ static __inline__ void atomic_set_mask(unsigned long mask, atomic_t *addr)
313#define smp_mb__before_atomic_inc() barrier() 313#define smp_mb__before_atomic_inc() barrier()
314#define smp_mb__after_atomic_inc() barrier() 314#define smp_mb__after_atomic_inc() barrier()
315 315
316#include <asm-generic/atomic.h>
316#endif /* _ASM_M32R_ATOMIC_H */ 317#endif /* _ASM_M32R_ATOMIC_H */
diff --git a/include/asm-m32r/cacheflush.h b/include/asm-m32r/cacheflush.h
index 46fc4c325108..e57427b6e249 100644
--- a/include/asm-m32r/cacheflush.h
+++ b/include/asm-m32r/cacheflush.h
@@ -7,7 +7,7 @@
7extern void _flush_cache_all(void); 7extern void _flush_cache_all(void);
8extern void _flush_cache_copyback_all(void); 8extern void _flush_cache_copyback_all(void);
9 9
10#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) 10#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
11#define flush_cache_all() do { } while (0) 11#define flush_cache_all() do { } while (0)
12#define flush_cache_mm(mm) do { } while (0) 12#define flush_cache_mm(mm) do { } while (0)
13#define flush_cache_range(vma, start, end) do { } while (0) 13#define flush_cache_range(vma, start, end) do { } while (0)
diff --git a/include/asm-m32r/irq.h b/include/asm-m32r/irq.h
index 8ed77968ecb4..ca943954572a 100644
--- a/include/asm-m32r/irq.h
+++ b/include/asm-m32r/irq.h
@@ -65,6 +65,22 @@
65#define NR_IRQS \ 65#define NR_IRQS \
66 (OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \ 66 (OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \
67 + OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ) 67 + OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ)
68
69#elif defined(CONFIG_PLAT_M32104UT)
70/*
71 * IRQ definitions for M32104UT
72 * M32104 Chip: 64 interrupts
73 * ICU of M32104UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
74 */
75#define M32104UT_NUM_CPU_IRQ (64)
76#define M32104UT_NUM_PLD_IRQ (32)
77#define M32104UT_IRQ_BASE 0
78#define M32104UT_CPU_IRQ_BASE M32104UT_IRQ_BASE
79#define M32104UT_PLD_IRQ_BASE (M32104UT_CPU_IRQ_BASE + M32104UT_NUM_CPU_IRQ)
80
81#define NR_IRQS \
82 (M32104UT_NUM_CPU_IRQ + M32104UT_NUM_PLD_IRQ)
83
68#else 84#else
69#define NR_IRQS 64 85#define NR_IRQS 64
70#endif 86#endif
diff --git a/include/asm-m32r/m32102.h b/include/asm-m32r/m32102.h
index cb98101f4f6e..a1f0d1fe9eb8 100644
--- a/include/asm-m32r/m32102.h
+++ b/include/asm-m32r/m32102.h
@@ -11,7 +11,11 @@
11/*======================================================================* 11/*======================================================================*
12 * Special Function Register 12 * Special Function Register
13 *======================================================================*/ 13 *======================================================================*/
14#if !defined(CONFIG_CHIP_M32104)
14#define M32R_SFR_OFFSET (0x00E00000) /* 0x00E00000-0x00EFFFFF 1[MB] */ 15#define M32R_SFR_OFFSET (0x00E00000) /* 0x00E00000-0x00EFFFFF 1[MB] */
16#else
17#define M32R_SFR_OFFSET (0x00700000) /* 0x00700000-0x007FFFFF 1[MB] */
18#endif
15 19
16/* 20/*
17 * Clock and Power Management registers. 21 * Clock and Power Management registers.
@@ -100,7 +104,7 @@
100#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */ 104#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
101#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */ 105#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
102 106
103#ifdef CONFIG_CHIP_M32700 107#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32104)
104#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */ 108#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */
105#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */ 109#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */
106#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */ 110#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */
@@ -113,7 +117,7 @@
113#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */ 117#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */
114#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */ 118#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */
115#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */ 119#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */
116#else /* not CONFIG_CHIP_M32700 */ 120#else /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */
117#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */ 121#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */
118#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */ 122#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */
119#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */ 123#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */
@@ -126,7 +130,7 @@
126#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */ 130#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */
127#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */ 131#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */
128#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */ 132#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */
129#endif /* not CONFIG_CHIP_M32700 */ 133#endif /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */
130 134
131#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */ 135#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */
132#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */ 136#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */
@@ -241,8 +245,24 @@
241#define M32R_IRQ_MFT1 (17) /* MFT1 */ 245#define M32R_IRQ_MFT1 (17) /* MFT1 */
242#define M32R_IRQ_MFT2 (18) /* MFT2 */ 246#define M32R_IRQ_MFT2 (18) /* MFT2 */
243#define M32R_IRQ_MFT3 (19) /* MFT3 */ 247#define M32R_IRQ_MFT3 (19) /* MFT3 */
244#define M32R_IRQ_MFT4 (20) /* MFT4 */ 248#ifdef CONFIG_CHIP_M32104
245#define M32R_IRQ_MFT5 (21) /* MFT5 */ 249#define M32R_IRQ_MFTX0 (24) /* MFTX0 */
250#define M32R_IRQ_MFTX1 (25) /* MFTX1 */
251#define M32R_IRQ_DMA0 (32) /* DMA0 */
252#define M32R_IRQ_DMA1 (33) /* DMA1 */
253#define M32R_IRQ_DMA2 (34) /* DMA2 */
254#define M32R_IRQ_DMA3 (35) /* DMA3 */
255#define M32R_IRQ_SIO0_R (40) /* SIO0 send */
256#define M32R_IRQ_SIO0_S (41) /* SIO0 receive */
257#define M32R_IRQ_SIO1_R (42) /* SIO1 send */
258#define M32R_IRQ_SIO1_S (43) /* SIO1 receive */
259#define M32R_IRQ_SIO2_R (44) /* SIO2 send */
260#define M32R_IRQ_SIO2_S (45) /* SIO2 receive */
261#define M32R_IRQ_SIO3_R (46) /* SIO3 send */
262#define M32R_IRQ_SIO3_S (47) /* SIO3 receive */
263#define M32R_IRQ_ADC (56) /* ADC */
264#define M32R_IRQ_PC (57) /* PC */
265#else /* ! M32104 */
246#define M32R_IRQ_DMA0 (32) /* DMA0 */ 266#define M32R_IRQ_DMA0 (32) /* DMA0 */
247#define M32R_IRQ_DMA1 (33) /* DMA1 */ 267#define M32R_IRQ_DMA1 (33) /* DMA1 */
248#define M32R_IRQ_SIO0_R (48) /* SIO0 send */ 268#define M32R_IRQ_SIO0_R (48) /* SIO0 send */
@@ -255,6 +275,7 @@
255#define M32R_IRQ_SIO3_S (55) /* SIO3 receive */ 275#define M32R_IRQ_SIO3_S (55) /* SIO3 receive */
256#define M32R_IRQ_SIO4_R (56) /* SIO4 send */ 276#define M32R_IRQ_SIO4_R (56) /* SIO4 send */
257#define M32R_IRQ_SIO4_S (57) /* SIO4 receive */ 277#define M32R_IRQ_SIO4_S (57) /* SIO4 receive */
278#endif /* ! M32104 */
258 279
259#ifdef CONFIG_SMP 280#ifdef CONFIG_SMP
260#define M32R_IRQ_IPI0 (56) 281#define M32R_IRQ_IPI0 (56)
@@ -281,15 +302,12 @@
281#define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP) 302#define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP)
282#define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP) 303#define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP)
283 304
305#endif /* CONFIG_SMP */
306
284#ifndef __ASSEMBLY__ 307#ifndef __ASSEMBLY__
285/* For NETDEV WATCHDOG */
286typedef struct { 308typedef struct {
287 unsigned long icucr; /* ICU Control Register */ 309 unsigned long icucr; /* ICU Control Register */
288} icu_data_t; 310} icu_data_t;
289
290extern icu_data_t icu_data[];
291#endif 311#endif
292 312
293#endif /* CONFIG_SMP */
294
295#endif /* _M32102_H_ */ 313#endif /* _M32102_H_ */
diff --git a/include/asm-m32r/m32104ut/m32104ut_pld.h b/include/asm-m32r/m32104ut/m32104ut_pld.h
new file mode 100644
index 000000000000..a4eac20553df
--- /dev/null
+++ b/include/asm-m32r/m32104ut/m32104ut_pld.h
@@ -0,0 +1,163 @@
1/*
2 * include/asm/m32104ut/m32104ut_pld.h
3 *
4 * Definitions for Programable Logic Device(PLD) on M32104UT board.
5 * Based on m32700ut_pld.h
6 *
7 * Copyright (c) 2002 Takeo Takahashi
8 * Copyright (c) 2005 Naoto Sugai
9 *
10 * This file is subject to the terms and conditions of the GNU General
11 * Public License. See the file "COPYING" in the main directory of
12 * this archive for more details.
13 */
14
15#ifndef _M32104UT_M32104UT_PLD_H
16#define _M32104UT_M32104UT_PLD_H
17
18#include <linux/config.h>
19
20#if defined(CONFIG_PLAT_M32104UT)
21#define PLD_PLAT_BASE 0x02c00000
22#else
23#error "no platform configuration"
24#endif
25
26#ifndef __ASSEMBLY__
27/*
28 * C functions use non-cache address.
29 */
30#define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
31#define __reg8 (volatile unsigned char *)
32#define __reg16 (volatile unsigned short *)
33#define __reg32 (volatile unsigned int *)
34#else
35#define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET)
36#define __reg8
37#define __reg16
38#define __reg32
39#endif /* __ASSEMBLY__ */
40
41/* CFC */
42#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
43#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
44#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
45#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
46
47/* MMC */
48#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
49#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
50#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
51#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
52#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
53#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
54#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
55#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
56#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
57#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
58#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
59#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
60
61/* ICU
62 * ICUISTS: status register
63 * ICUIREQ0: request register
64 * ICUIREQ1: request register
65 * ICUCR3: control register for CFIREQ# interrupt
66 * ICUCR4: control register for CFC Card insert interrupt
67 * ICUCR5: control register for CFC Card eject interrupt
68 * ICUCR6: control register for external interrupt
69 * ICUCR11: control register for MMC Card insert/eject interrupt
70 * ICUCR13: control register for SC error interrupt
71 * ICUCR14: control register for SC receive interrupt
72 * ICUCR15: control register for SC send interrupt
73 */
74
75#define PLD_IRQ_INT0 (M32104UT_PLD_IRQ_BASE + 0) /* None */
76#define PLD_IRQ_CFIREQ (M32104UT_PLD_IRQ_BASE + 3) /* CF IREQ */
77#define PLD_IRQ_CFC_INSERT (M32104UT_PLD_IRQ_BASE + 4) /* CF Insert */
78#define PLD_IRQ_CFC_EJECT (M32104UT_PLD_IRQ_BASE + 5) /* CF Eject */
79#define PLD_IRQ_EXINT (M32104UT_PLD_IRQ_BASE + 6) /* EXINT */
80#define PLD_IRQ_MMCCARD (M32104UT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */
81#define PLD_IRQ_SC_ERROR (M32104UT_PLD_IRQ_BASE + 13) /* SC error */
82#define PLD_IRQ_SC_RCV (M32104UT_PLD_IRQ_BASE + 14) /* SC receive */
83#define PLD_IRQ_SC_SND (M32104UT_PLD_IRQ_BASE + 15) /* SC send */
84
85#define PLD_ICUISTS __reg16(PLD_BASE + 0x8002)
86#define PLD_ICUISTS_VECB_MASK (0xf000)
87#define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK)
88#define PLD_ICUISTS_ISN_MASK (0x07c0)
89#define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK)
90#define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104)
91#define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106)
92#define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108)
93#define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a)
94#define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114)
95#define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118)
96#define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a)
97#define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c)
98#define PLD_ICUCR_IEN (0x1000)
99#define PLD_ICUCR_IREQ (0x0100)
100#define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */
101#define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */
102#define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */
103#define PLD_ICUCR_ISMOD03 (0x0030) /* High level */
104#define PLD_ICUCR_ILEVEL0 (0x0000)
105#define PLD_ICUCR_ILEVEL1 (0x0001)
106#define PLD_ICUCR_ILEVEL2 (0x0002)
107#define PLD_ICUCR_ILEVEL3 (0x0003)
108#define PLD_ICUCR_ILEVEL4 (0x0004)
109#define PLD_ICUCR_ILEVEL5 (0x0005)
110#define PLD_ICUCR_ILEVEL6 (0x0006)
111#define PLD_ICUCR_ILEVEL7 (0x0007)
112
113/* Power Control of MMC and CF */
114#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
115#define PLD_CPCR_CDP 0x0001
116
117/* LED Control
118 *
119 * 1: DIP swich side
120 * 2: Reset switch side
121 */
122#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
123#define PLD_IOLED_1_ON 0x001
124#define PLD_IOLED_1_OFF 0x000
125#define PLD_IOLED_2_ON 0x002
126#define PLD_IOLED_2_OFF 0x000
127
128/* DIP Switch
129 * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
130 * 1: -
131 * 2: -
132 * 3: -
133 */
134#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
135#define PLD_IOSWSTS_IOSW2 0x0200
136#define PLD_IOSWSTS_IOSW1 0x0100
137#define PLD_IOSWSTS_IOWP0 0x0001
138
139/* CRC */
140#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
141#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
142#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
143#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
144#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
145#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
146
147/* RTC */
148#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
149#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
150#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
151#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
152#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
153
154/* SIM Card */
155#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
156#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
157#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
158#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
159#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
160#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
161#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
162
163#endif /* _M32104UT_M32104UT_PLD_H */
diff --git a/include/asm-m32r/m32r.h b/include/asm-m32r/m32r.h
index ec142be00862..b133ca61acf1 100644
--- a/include/asm-m32r/m32r.h
+++ b/include/asm-m32r/m32r.h
@@ -14,7 +14,7 @@
14#include <asm/m32r_mp_fpga.h> 14#include <asm/m32r_mp_fpga.h>
15#elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \ 15#elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
16 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \ 16 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
17 || defined(CONFIG_CHIP_OPSP) 17 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
18#include <asm/m32102.h> 18#include <asm/m32102.h>
19#endif 19#endif
20 20
@@ -43,6 +43,10 @@
43#include <asm/m32700ut/m32700ut_pld.h> 43#include <asm/m32700ut/m32700ut_pld.h>
44#endif 44#endif
45 45
46#if defined(CONFIG_PLAT_M32104UT)
47#include <asm/m32104ut/m32104ut_pld.h>
48#endif /* CONFIG_PLAT_M32104 */
49
46/* 50/*
47 * M32R Register 51 * M32R Register
48 */ 52 */
@@ -122,7 +126,7 @@
122 126
123#include <asm/page.h> 127#include <asm/page.h>
124#ifdef CONFIG_MMU 128#ifdef CONFIG_MMU
125#define NONCACHE_OFFSET __PAGE_OFFSET+0x20000000 129#define NONCACHE_OFFSET (__PAGE_OFFSET + 0x20000000)
126#else 130#else
127#define NONCACHE_OFFSET __PAGE_OFFSET 131#define NONCACHE_OFFSET __PAGE_OFFSET
128#endif /* CONFIG_MMU */ 132#endif /* CONFIG_MMU */
diff --git a/include/asm-m32r/mman.h b/include/asm-m32r/mman.h
index 011f6d9ec5cc..12e29747bc84 100644
--- a/include/asm-m32r/mman.h
+++ b/include/asm-m32r/mman.h
@@ -37,6 +37,7 @@
37#define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */ 37#define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */
38#define MADV_WILLNEED 0x3 /* pre-fault pages */ 38#define MADV_WILLNEED 0x3 /* pre-fault pages */
39#define MADV_DONTNEED 0x4 /* discard these pages */ 39#define MADV_DONTNEED 0x4 /* discard these pages */
40#define MADV_REMOVE 0x5 /* remove these pages & resources */
40 41
41/* compatibility flags */ 42/* compatibility flags */
42#define MAP_ANON MAP_ANONYMOUS 43#define MAP_ANON MAP_ANONYMOUS
diff --git a/include/asm-m32r/system.h b/include/asm-m32r/system.h
index 5eee832b73a0..dcf619a0a0b0 100644
--- a/include/asm-m32r/system.h
+++ b/include/asm-m32r/system.h
@@ -69,12 +69,12 @@
69} while(0) 69} while(0)
70 70
71/* Interrupt Control */ 71/* Interrupt Control */
72#if !defined(CONFIG_CHIP_M32102) 72#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
73#define local_irq_enable() \ 73#define local_irq_enable() \
74 __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory") 74 __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory")
75#define local_irq_disable() \ 75#define local_irq_disable() \
76 __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory") 76 __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory")
77#else /* CONFIG_CHIP_M32102 */ 77#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
78static inline void local_irq_enable(void) 78static inline void local_irq_enable(void)
79{ 79{
80 unsigned long tmpreg; 80 unsigned long tmpreg;
@@ -96,7 +96,7 @@ static inline void local_irq_disable(void)
96 "mvtc %0, psw \n\t" 96 "mvtc %0, psw \n\t"
97 : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory"); 97 : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory");
98} 98}
99#endif /* CONFIG_CHIP_M32102 */ 99#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
100 100
101#define local_save_flags(x) \ 101#define local_save_flags(x) \
102 __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */) 102 __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */)
@@ -105,13 +105,13 @@ static inline void local_irq_disable(void)
105 __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \ 105 __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \
106 : "r" (x) : "cbit", "memory") 106 : "r" (x) : "cbit", "memory")
107 107
108#if !defined(CONFIG_CHIP_M32102) 108#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
109#define local_irq_save(x) \ 109#define local_irq_save(x) \
110 __asm__ __volatile__( \ 110 __asm__ __volatile__( \
111 "mvfc %0, psw; \n\t" \ 111 "mvfc %0, psw; \n\t" \
112 "clrpsw #0x40 -> nop; \n\t" \ 112 "clrpsw #0x40 -> nop; \n\t" \
113 : "=r" (x) : /* no input */ : "memory") 113 : "=r" (x) : /* no input */ : "memory")
114#else /* CONFIG_CHIP_M32102 */ 114#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
115#define local_irq_save(x) \ 115#define local_irq_save(x) \
116 ({ \ 116 ({ \
117 unsigned long tmpreg; \ 117 unsigned long tmpreg; \
@@ -124,7 +124,7 @@ static inline void local_irq_disable(void)
124 : "=r" (x), "=&r" (tmpreg) \ 124 : "=r" (x), "=&r" (tmpreg) \
125 : : "cbit", "memory"); \ 125 : : "cbit", "memory"); \
126 }) 126 })
127#endif /* CONFIG_CHIP_M32102 */ 127#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
128 128
129#define irqs_disabled() \ 129#define irqs_disabled() \
130 ({ \ 130 ({ \
diff --git a/include/asm-m32r/unistd.h b/include/asm-m32r/unistd.h
index ac399e1f7bc0..39be87ca2a5a 100644
--- a/include/asm-m32r/unistd.h
+++ b/include/asm-m32r/unistd.h
@@ -319,7 +319,7 @@ type name(void) \
319register long __scno __asm__ ("r7") = __NR_##name; \ 319register long __scno __asm__ ("r7") = __NR_##name; \
320register long __res __asm__("r0"); \ 320register long __res __asm__("r0"); \
321__asm__ __volatile__ (\ 321__asm__ __volatile__ (\
322 "trap #" SYSCALL_VECTOR \ 322 "trap #" SYSCALL_VECTOR "|| nop"\
323 : "=r" (__res) \ 323 : "=r" (__res) \
324 : "r" (__scno) \ 324 : "r" (__scno) \
325 : "memory"); \ 325 : "memory"); \
@@ -332,7 +332,7 @@ type name(type1 arg1) \
332register long __scno __asm__ ("r7") = __NR_##name; \ 332register long __scno __asm__ ("r7") = __NR_##name; \
333register long __res __asm__ ("r0") = (long)(arg1); \ 333register long __res __asm__ ("r0") = (long)(arg1); \
334__asm__ __volatile__ (\ 334__asm__ __volatile__ (\
335 "trap #" SYSCALL_VECTOR \ 335 "trap #" SYSCALL_VECTOR "|| nop"\
336 : "=r" (__res) \ 336 : "=r" (__res) \
337 : "r" (__scno), "0" (__res) \ 337 : "r" (__scno), "0" (__res) \
338 : "memory"); \ 338 : "memory"); \
@@ -346,7 +346,7 @@ register long __scno __asm__ ("r7") = __NR_##name; \
346register long __arg2 __asm__ ("r1") = (long)(arg2); \ 346register long __arg2 __asm__ ("r1") = (long)(arg2); \
347register long __res __asm__ ("r0") = (long)(arg1); \ 347register long __res __asm__ ("r0") = (long)(arg1); \
348__asm__ __volatile__ (\ 348__asm__ __volatile__ (\
349 "trap #" SYSCALL_VECTOR \ 349 "trap #" SYSCALL_VECTOR "|| nop"\
350 : "=r" (__res) \ 350 : "=r" (__res) \
351 : "r" (__scno), "0" (__res), "r" (__arg2) \ 351 : "r" (__scno), "0" (__res), "r" (__arg2) \
352 : "memory"); \ 352 : "memory"); \
@@ -361,7 +361,7 @@ register long __arg3 __asm__ ("r2") = (long)(arg3); \
361register long __arg2 __asm__ ("r1") = (long)(arg2); \ 361register long __arg2 __asm__ ("r1") = (long)(arg2); \
362register long __res __asm__ ("r0") = (long)(arg1); \ 362register long __res __asm__ ("r0") = (long)(arg1); \
363__asm__ __volatile__ (\ 363__asm__ __volatile__ (\
364 "trap #" SYSCALL_VECTOR \ 364 "trap #" SYSCALL_VECTOR "|| nop"\
365 : "=r" (__res) \ 365 : "=r" (__res) \
366 : "r" (__scno), "0" (__res), "r" (__arg2), \ 366 : "r" (__scno), "0" (__res), "r" (__arg2), \
367 "r" (__arg3) \ 367 "r" (__arg3) \
@@ -378,7 +378,7 @@ register long __arg3 __asm__ ("r2") = (long)(arg3); \
378register long __arg2 __asm__ ("r1") = (long)(arg2); \ 378register long __arg2 __asm__ ("r1") = (long)(arg2); \
379register long __res __asm__ ("r0") = (long)(arg1); \ 379register long __res __asm__ ("r0") = (long)(arg1); \
380__asm__ __volatile__ (\ 380__asm__ __volatile__ (\
381 "trap #" SYSCALL_VECTOR \ 381 "trap #" SYSCALL_VECTOR "|| nop"\
382 : "=r" (__res) \ 382 : "=r" (__res) \
383 : "r" (__scno), "0" (__res), "r" (__arg2), \ 383 : "r" (__scno), "0" (__res), "r" (__arg2), \
384 "r" (__arg3), "r" (__arg4) \ 384 "r" (__arg3), "r" (__arg4) \
@@ -397,7 +397,7 @@ register long __arg3 __asm__ ("r2") = (long)(arg3); \
397register long __arg2 __asm__ ("r1") = (long)(arg2); \ 397register long __arg2 __asm__ ("r1") = (long)(arg2); \
398register long __res __asm__ ("r0") = (long)(arg1); \ 398register long __res __asm__ ("r0") = (long)(arg1); \
399__asm__ __volatile__ (\ 399__asm__ __volatile__ (\
400 "trap #" SYSCALL_VECTOR \ 400 "trap #" SYSCALL_VECTOR "|| nop"\
401 : "=r" (__res) \ 401 : "=r" (__res) \
402 : "r" (__scno), "0" (__res), "r" (__arg2), \ 402 : "r" (__scno), "0" (__res), "r" (__arg2), \
403 "r" (__arg3), "r" (__arg4), "r" (__arg5) \ 403 "r" (__arg3), "r" (__arg4), "r" (__arg5) \
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 06:33:22 -0500