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-rw-r--r--include/asm-m32r/s1d13806.h199
1 files changed, 0 insertions, 199 deletions
diff --git a/include/asm-m32r/s1d13806.h b/include/asm-m32r/s1d13806.h
deleted file mode 100644
index 248d36a82d79..000000000000
--- a/include/asm-m32r/s1d13806.h
+++ /dev/null
@@ -1,199 +0,0 @@
1//----------------------------------------------------------------------------
2//
3// File generated by S1D13806CFG.EXE
4//
5// Copyright (c) 2000,2001 Epson Research and Development, Inc.
6// All rights reserved.
7//
8//----------------------------------------------------------------------------
9
10// Panel: (active) 640x480 77Hz STN Single 8-bit (PCLK=CLKI=25.175MHz)
11// Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=33.333MHz)
12
13#define SWIVEL_VIEW 0 /* 0:none, 1:90 not completed */
14
15static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
16
17 {0x0001,0x00}, // Miscellaneous Register
18 {0x01FC,0x00}, // Display Mode Register
19#if defined(CONFIG_PLAT_MAPPI)
20 {0x0004,0x00}, // General IO Pins Configuration Register 0
21 {0x0005,0x00}, // General IO Pins Configuration Register 1
22 {0x0008,0x00}, // General IO Pins Control Register 0
23 {0x0009,0x00}, // General IO Pins Control Register 1
24 {0x0010,0x00}, // Memory Clock Configuration Register
25 {0x0014,0x00}, // LCD Pixel Clock Configuration Register
26 {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register
27 {0x001C,0x00}, // MediaPlug Clock Configuration Register
28/*
29 * .. 10MHz: 0x00
30 * .. 30MHz: 0x01
31 * 30MHz ..: 0x02
32 */
33 {0x001E,0x02}, // CPU To Memory Wait State Select Register
34 {0x0021,0x02}, // DRAM Refresh Rate Register
35 {0x002A,0x11}, // DRAM Timings Control Register 0
36 {0x002B,0x13}, // DRAM Timings Control Register 1
37 {0x0020,0x80}, // Memory Configuration Register
38 {0x0030,0x25}, // Panel Type Register
39 {0x0031,0x00}, // MOD Rate Register
40 {0x0032,0x4F}, // LCD Horizontal Display Width Register
41 {0x0034,0x12}, // LCD Horizontal Non-Display Period Register
42 {0x0035,0x01}, // TFT FPLINE Start Position Register
43 {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
44 {0x0038,0xDF}, // LCD Vertical Display Height Register 0
45 {0x0039,0x01}, // LCD Vertical Display Height Register 1
46 {0x003A,0x2C}, // LCD Vertical Non-Display Period Register
47 {0x003B,0x0A}, // TFT FPFRAME Start Position Register
48 {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
49
50 {0x0041,0x00}, // LCD Miscellaneous Register
51 {0x0042,0x00}, // LCD Display Start Address Register 0
52 {0x0043,0x00}, // LCD Display Start Address Register 1
53 {0x0044,0x00}, // LCD Display Start Address Register 2
54
55#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
56 {0x0004,0x07}, // GPIO[0:7] direction
57 {0x0005,0x00}, // GPIO[8:12] direction
58 {0x0008,0x00}, // GPIO[0:7] data
59 {0x0009,0x00}, // GPIO[8:12] data
60 {0x0008,0x04}, // LCD panel Vcc on
61 {0x0008,0x05}, // LCD panel reset
62 {0x0010,0x01}, // Memory Clock Configuration Register
63 {0x0014,0x30}, // LCD Pixel Clock Configuration Register (CLKI 22MHz/4)
64 {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register
65 {0x001C,0x00}, // MediaPlug Clock Configuration Register(10MHz)
66 {0x001E,0x00}, // CPU To Memory Wait State Select Register
67 {0x0020,0x80}, // Memory Configuration Register
68 {0x0021,0x03}, // DRAM Refresh Rate Register
69 {0x002A,0x00}, // DRAM Timings Control Register 0
70 {0x002B,0x01}, // DRAM Timings Control Register 1
71 {0x0030,0x25}, // Panel Type Register
72 {0x0031,0x00}, // MOD Rate Register
73 {0x0032,0x1d}, // LCD Horizontal Display Width Register
74 {0x0034,0x05}, // LCD Horizontal Non-Display Period Register
75 {0x0035,0x01}, // TFT FPLINE Start Position Register
76 {0x0036,0x01}, // TFT FPLINE Pulse Width Register
77 {0x0038,0x3F}, // LCD Vertical Display Height Register 0
78 {0x0039,0x01}, // LCD Vertical Display Height Register 1
79 {0x003A,0x0b}, // LCD Vertical Non-Display Period Register
80 {0x003B,0x07}, // TFT FPFRAME Start Position Register
81 {0x003C,0x02}, // TFT FPFRAME Pulse Width Register
82
83 {0x0041,0x00}, // LCD Miscellaneous Register
84#if (SWIVEL_VIEW == 0)
85 {0x0042,0x00}, // LCD Display Start Address Register 0
86 {0x0043,0x00}, // LCD Display Start Address Register 1
87 {0x0044,0x00}, // LCD Display Start Address Register 2
88
89#elif (SWIVEL_VIEW == 1)
90 // 1024 - W(320) = 0x2C0
91 {0x0042,0xC0}, // LCD Display Start Address Register 0
92 {0x0043,0x02}, // LCD Display Start Address Register 1
93 {0x0044,0x00}, // LCD Display Start Address Register 2
94 // 1024
95 {0x0046,0x00}, // LCD Memory Address Offset Register 0
96 {0x0047,0x02}, // LCD Memory Address Offset Register 1
97#else
98#error unsupported SWIVEL_VIEW mode
99#endif
100#else
101#error no platform configuration
102#endif /* CONFIG_PLAT_XXX */
103
104 {0x0048,0x00}, // LCD Pixel Panning Register
105 {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
106 {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
107 {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
108 {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
109 {0x0053,0x01}, // CRT/TV HRTC Start Position Register
110 {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
111 {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
112 {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
113 {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
114 {0x0059,0x09}, // CRT/TV VRTC Start Position Register
115 {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
116 {0x005B,0x10}, // TV Output Control Register
117
118 {0x0062,0x00}, // CRT/TV Display Start Address Register 0
119 {0x0063,0x00}, // CRT/TV Display Start Address Register 1
120 {0x0064,0x00}, // CRT/TV Display Start Address Register 2
121
122 {0x0068,0x00}, // CRT/TV Pixel Panning Register
123 {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
124 {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
125 {0x0070,0x00}, // LCD Ink/Cursor Control Register
126 {0x0071,0x01}, // LCD Ink/Cursor Start Address Register
127 {0x0072,0x00}, // LCD Cursor X Position Register 0
128 {0x0073,0x00}, // LCD Cursor X Position Register 1
129 {0x0074,0x00}, // LCD Cursor Y Position Register 0
130 {0x0075,0x00}, // LCD Cursor Y Position Register 1
131 {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
132 {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
133 {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
134 {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
135 {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
136 {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
137 {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
138 {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
139 {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register
140 {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
141 {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
142 {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
143 {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
144 {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
145 {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
146 {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
147 {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
148 {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
149 {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
150 {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
151 {0x0100,0x00}, // BitBlt Control Register 0
152 {0x0101,0x00}, // BitBlt Control Register 1
153 {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
154 {0x0103,0x00}, // BitBlt Operation Register
155 {0x0104,0x00}, // BitBlt Source Start Address Register 0
156 {0x0105,0x00}, // BitBlt Source Start Address Register 1
157 {0x0106,0x00}, // BitBlt Source Start Address Register 2
158 {0x0108,0x00}, // BitBlt Destination Start Address Register 0
159 {0x0109,0x00}, // BitBlt Destination Start Address Register 1
160 {0x010A,0x00}, // BitBlt Destination Start Address Register 2
161 {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
162 {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
163 {0x0110,0x00}, // BitBlt Width Register 0
164 {0x0111,0x00}, // BitBlt Width Register 1
165 {0x0112,0x00}, // BitBlt Height Register 0
166 {0x0113,0x00}, // BitBlt Height Register 1
167 {0x0114,0x00}, // BitBlt Background Color Register 0
168 {0x0115,0x00}, // BitBlt Background Color Register 1
169 {0x0118,0x00}, // BitBlt Foreground Color Register 0
170 {0x0119,0x00}, // BitBlt Foreground Color Register 1
171 {0x01E0,0x00}, // Look-Up Table Mode Register
172 {0x01E2,0x00}, // Look-Up Table Address Register
173 {0x01F0,0x10}, // Power Save Configuration Register
174 {0x01F1,0x00}, // Power Save Status Register
175 {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
176#if (SWIVEL_VIEW == 0)
177 {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
178#elif (SWIVEL_VIEW == 1)
179 {0x01FC,0x41}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
180#else
181#error unsupported SWIVEL_VIEW mode
182#endif /* SWIVEL_VIEW */
183
184#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
185 {0x0008,0x07}, // LCD panel Vdd & Vg on
186#endif
187
188 {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
189#if defined(CONFIG_PLAT_MAPPI)
190 {0x0046,0x80}, // LCD Memory Address Offset Register 0
191 {0x0047,0x02}, // LCD Memory Address Offset Register 1
192#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
193 {0x0046,0xf0}, // LCD Memory Address Offset Register 0
194 {0x0047,0x00}, // LCD Memory Address Offset Register 1
195#endif
196 {0x0060,0x05}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
197 {0x0066,0x80}, // CRT/TV Memory Address Offset Register 0 // takeo
198 {0x0067,0x02}, // CRT/TV Memory Address Offset Register 1
199};
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-15 05:57:46 -0500